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This paper aims to present a design of a single power supply, low voltage (1.2) high performance operational amplifier using 0.13 μm technology whose characteristics are superior compared to the other designs available in the literature.

The authors set out to design an operational amplifier whose characteristics will be superior to the current available designs in the literature. Because of potential applications, a single 1.2 V supply was used. The layout was obtained using Microwind 0.13 μm technology. The design was tested using PSPICE Version 10.0. Various amplifier parameters were obtained and are compared with the other single supply, low voltage amplifiers available in the literature.

The presented amplifier has better characteristics such as open loop gain, power supply rejection ratio, common mode rejection ratio, etc.

Since, 0.13 μm, 1.2 V technology has become standard in digital VLSI design, there is a great need for high performance operational amplifiers that operate off of 1.2 V for mixed signal applications in such areas as mobile phones.

The presented amplifier has better characteristics compared to few 1.2 V supply voltage amplifiers available in the literature.

The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.

To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.

Measurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.

The strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.

Multistage amplifiers require a reliable frequency compensation solution to remain stable in a closed-loop configuration. A frequency compensation scheme creates an inner negative feedback loop amongst different amplifying stages and shapes the frequency response such that an unconditionally stable single-pole amplifier results for closed-loop operation. The frequency compensation loop is thus responsible for the placement of the poles and zeros and the final stability of multistage amplifiers. An amplifier incorporating a sophisticated frequency compensation network cannot be, however, analyzed in the presence of a complex ac feedback loop. The purpose of this study is to provide a reliable model for the compensation loop of multistage amplifiers at the higher frequencies.

In this paper, the major part of the amplifier, including a two-port network comprising the compensation network, is characterized using a reliable feedback model.

The model integrates all the frequency-dependent components of the frequency compensation network, and it can evaluate the nondominant real or complex poles of an amplifier.

The reliability of the proposed model is verified through analysis of the frequency response of the amplifiers and by comparing the analytic results with the simulation results in standard CMOS process.

In this paper, we study the effect on the performance of a single supply low voltage operational amplifier due to such a mismatch.

We start with a given set of specifications and design a MOSFET based operational amplifier meeting those specifications. We then compute various parameters of the operational amplifier using PSPICE to verify that the amplifier meets the specifications. We create mismatch in three characteristics of differential pair MOSFETs: zero biased threshold voltage (V_th0), channel length (L) and process transconductance parameter (K). The effect of the mismatch on two performance parameters: (a) differential mode gain and (b) output DC voltage is then studied.

The effects of mismatch in MOSFET characteristics on the performance of single supply low voltage operational amplifiers are studied. Circuit designers can use the results to design operational amplifiers and other analog circuits to minimize the effects of such a mismatch on the performance of their circuits. In some cases, such a mismatch may even be desirable to obtain a desired performance from the circuit.

Circuit designers can use the results to design operational amplifiers and other analog circuits to minimize the effects of such a mismatch on the performance of their circuits.

Effect of mismatch of the transistor characteristics on the performance of circuits rarely reported in literature. This study is presented to aid circuit designers in designing circuits with enhanced performance.

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

Fiber nonlinearities are anticipated to impose transmission limitations due to the enhanced total interaction length in long‐haul dense wavelength division multiplexing (DWDM) optical transmission systems. The purpose of this paper is to analytically study the combined effect of stimulated Raman scattering (SRS) and four‐wave mixing (FWM) in the presence of amplified spontaneous emission (ASE) noise generated by erbium‐doped fiber amplifiers (EDFAs).

The paper presents analytical analysis of DWDM optical transmission systems in the presence of two significant fiber nonlinearities (SRS and FWM).

Simple expressions are derived to study the dependence of signal‐to‐noise ratio (SNR) on the amplifier spacing between two consecutive amplifiers.

The authors have analytically studied the combined effect of SRS and FWM in the presence of ASE noise generated by EDFAs. The novelty of the work is that it has considered all the three factors simultaneously and the expressions are derived for calculation of SNR.

The purpose of this paper is to demonstrate an effective and faster numerical solution for nonlinear‐coupled differential equations describing fiber amplifiers which have no explicit solution. MATLAB boundary value problem (BVP) solver of bvp6c function is addressed for the solution.

Coding method with the bvp6c is introduced, signal evolution, threshold calculation method is introduced, gain and noise figure are plotted and superiority of the bvp6c solver is compared with the Newton‐Raphson method.

bvp6c function appears to be an effective tool for the solution fiber amplifier equations and can be used for different pump configurations of BFAs and RFAs. The excellent agreement between the proposed and reported results shows the reliability of the proposed threshold power calculation method.

The paper eases the work of the fiber optic research community, who suffer from two point BVPs. Moreover, the stiffness of the signal evolution which is faced with high pump powers and/or long fiber lengths can be solved with continuation. This superiority of the solver can be used to overcome any stiff changes of the signals for the future studies.

The main outcome of this paper is the numerically calculation of the threshold values of fiber amplifiers without the necessity of the experiment. The robustness improvement of the solution is that the solver is able to solve the equations even with the poor guess values and the solution can be obtained without the necessity of analytical Jacobian matrix.

MATLAB bvp6c solver has proven to be effective for the numerical solution of nonlinear‐coupled intensity differential equations describing fiber amplifiers with two‐point boundary values. Beside the signal evolution, thresholds of Brillouin and Raman fiber amplifiers can also be calculated by using the proposed solver. This is a notable and promising improvement of the paper, at least from a fiber optic amplifier designer point of view.

The current generation of light wave systems benefit from increased transmission distance by using optical amplification and increased capacity by using dense wavelength division multiplexing (DWDM) technology. The reach of present systems is limited by the noise contributed by the used amplifiers, combined with nonlinear effects from transmission. This paper aims to address these issues.

The nature and extent of degradations in the optical DWDM systems due to these limiting factors have been discussed in this paper.

It has been learnt that stimulated Raman scattering (SRS), four wave mixing (FWM) and amplified spontaneous emission (ASE) are the important factors in optical DWDM systems. These factors limit the system capacity of the transmission systems drastically.

It can be concluded from the discussion that while designing an efficient DWDM system, an optimization of the channel separation and the amplifier separation is required to minimize the nonlinear effects (FWM and SRS) along with the ASE noise introduced by inline optical amplifications.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

The purpose of this paper is to provide a new hydrostatic actuator controlled by a piezoelectric piston pump and to reveal its characteristics.

In this paper, a piezoelectric pump with passive poppet valves and hydraulic displacement amplifier is designed as a new control component in a hydrostatic actuator for high actuation capacity. A component-level mathematical model is established to describe the system characteristics. Simulation verification for cases under typical conditions is implemented to evaluate the delivery behavior of the pump and the carrying ability of the actuator.

By using the displacement amplifier and the passive distributing valves, simulation demonstrates that the pump can deliver flow rate up to 3 L/min, and the actuator controlled by this pump can push an object weighing approximately 50 kg. In addition, it is particularly important to decide a proper amplification ratio of the amplifier in the pump for better actuation performance.

The piezoelectric pump presented in this paper has its potential to light hydrostatic actuator. The model constructed in this paper is valid for characteristic analysis and performance evaluation of this pump and actuators.