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The aim of this work is to examine the Hopfield network for the field programmable gate array (FPGA) cell placement.

Implementation of an algorithm in FPGA circuits requires synthesis, placement and the routing of logic cells. The placement takes the longest time for computation. Therefore, an algorithm for a run‐time reconfigurable system can be chosen from among earlier prepared algorithms. This paper presents a Hopfield neural network for solving the placement problem. The Hopfield network was also used for processing units in a parallel placement. Hardware implementation of presented solutions could accelerate the FPGA placement by orders of magnitude in comparison with placers executed on traditional computers. Hardware accelerators could also be applied to the design of other VLSI circuits. The simulation results for the FPGA placement are presented.

The Hopfield network and parallel placement give comparable placements with the method using a simulated annealing algorithm. The parallel placement enables a decrease in total number of neurons and neuron connections which are necessary for simultaneous placement of all cells in a circuit.

This work provides a starting‐point for further research under hardware realization of the cell placement by using the Hopfield network. The presented solutions can be used for FPGA, gate array, sea‐of‐gates circuits and standard cell circuits with the same size cells.

The Hopfield network is used for placement in real circuits, in which nets contain multiple terminals, and for processing units in a parallel placement.

To simulate large parasitic resistive networks, one must reduce the size of the circuit models through methods that are accurate and preserve terminal connectivity and network sparsity. The purpose here is to present such a method, which exploits concepts from graph theory in a systematic fashion.

The model order reduction problem is formulated for parasitic resistive networks through graph theory concepts and algorithms are presented based on the notion of vertex cut in order to reduce the size of electronic circuit models. Four variants of the basic method are proposed and their respective merits discussed.

The algorithms proposed enable the production of networks that are significantly smaller than those produced by earlier methods, in particular the method described in the report by Lenaers entitled “Model order reduction for large resistive networks”. The reduction in the number of resistors achieved through the algorithms is even more pronounced in the case of large networks.

The paper seems to be the first to make a systematic use of vertex cuts in order to reduce a parasitic resistive network.

The purpose of this paper is to provide the high-pass (HP) negative group delay (NGD) circuit based (RL) network. Synthesis and experimental investigation of HP-NGD circuit are developed.

The research work methodology is organized in three phases. The definition of the HP-NGD ideal specifications is introduced. The synthesis method allowing to determine the RL elements is developed. The validation results are discussed with comparison between the calculated model, simulation and measurement.

This paper shows a validation of the HP-NGD theory with responses confirming NGD optimal frequency, value and attenuation of about (9 kHz, −1.12 µs, −1.64 dB) and (21 kHz, −0.92 µs, −4.81 dB) are measured. The tested circuits have experimented NGD cut-off frequencies around 5 and 11.7 kHz.

The validity of the HP-NGD topology depends on the coil self-inductance resonance. The HP-NGD effect is susceptible to be penalized by the parasitic elements of the self.

The NGD circuit is usefully exploited in the electronic and communication system to reduce the undesired delay effect context. The NGD can be used to compensate the delay in any electronic devices and system.

Applications based on the NGD technology will be helpful in the communication, transportation and security research fields by reducing the delay inherent to any electronic circuit.

The originality of the paper concerns the synthesis formulations of the RL elements in function of the expected HP-NGD optimal frequency, value and attenuation. In addition, an original measurement technique of HP-NGD is also introduced.

First, know your network, its key points, the geographic nature of the business and how disaster can happen. Second, understand where the network bottlenecks are positioned. Several options are presented to reduce bottlenecks such as: permanent alternative paths, coterminous circuits, packet switching networks. Third, evaluate equipment redundancy, people redundancy, outsourcing, and multiple carriers. A network is considered “a disaster waiting to happen” which management must support via a DRP.

Many practical applications of neural networks require the identification of non‐linear deterministic systems or chaotic systems. In these cases the use of a network architecture known as locally recurrent neural network (LRNN) is often preferable in place of standard feedforward multi‐layer perceptron (MLP) networks, or of globally recurrent neural network. In this paper locally recurrent networks are used to simulate the behaviour of the Chua’s circuit that can be considered a paradigm for studying chaos. It is shown that such networks are able to identify the underlying link among the state variables of the Chua’s circuit. Moreover, they are able to behave like an autonomous Chua’s double scroll, showing a chaotic behaviour of the state variables obtainable through a suitable circuit elements choice.

Recently, the modelling and simulation of switched systems containing new nonlinear components in electronics and power electronics industry have gained importance. In this paper, both feed‐forward artificial neural networks (ANN) and adaptive network‐based fuzzy inference systems (ANFIS) have been applied to switched circuits and systems. Then their performances have been compared in this contribution by developed simulation programs. It has been shown that ANFIS require less training time and offer better performance than those of ANN. In addition, ANFIS using “clustering algorithm” to generate the rules and the numbers of membership functions gives a smaller number of parameters, better performance and less training time than those of ANFIS using “grid partition” to generate the rules. The work not only demonstrates the advantage of the ANFIS architecture using clustering algorithm but also highlights the advantages of the architecture for hardware realizations.

An electrical company is responsible for the maintenance of a transmission network of high voltage electricity. The maintenance schedule must be planned so as to minimize outage costs, taking into consideration various factors such as system security/reliability, system availability, and manpower utilization. With the rapid growth of organization, planning engineers are required to fulfill additional roles in order to increase productivity. To this end, a fast response and accurate mechanism is required to assist the planning engineers in dealing with the daily operation. This paper describes how a proposed maintenance schedule can be obtained automatically by the adoption of genetic algorithm. The main aim is to determine the maintenance schedule of circuit outage with minimizing the maintenance cost and maximizing the circuit availability under certain unavoidable system constraints. Further, an additional search mechanism called “final tuning search” is developed to enhance the system performance.

This is the final part of an abridged version of the previously unpublished writings of Paul Eisler, universally acknowledged as the inventor of the printed circuit board and many other technical innovations. The content of the extracts presented has concentrated mainly on Dr Eisler's efforts in the field of printed circuit technology, followed by a few details of some of his other areas of invention.

Telecommunications are fundamental to the online industry and this article seeks to place telecommunications networks within the context of information retrieval. The history of network development is discussed against a background and explanation of the various technical forms of telecommunications networks that existed at the beginning of the nineteen sixties and have since developed. The remainder of the paper examines the networking resources that have become available since 1984.

This paper aims to describe the effect of VoIP network architectures on the cost modelling of termination rates of VoIP services.

The study investigates and organises the arguments available in the technical and regulatory field related to VoIP networks and services in order to ascertain the possible impact of VoIP techniques, the provisioning of voice features in VoIP networks, and network interconnection issues on the cost of regulated VoIP services.

The information and analysis reveals how the provision of VoIP services is related to a number of issues that will have an effect on the cost of VoIP termination rates. In particular, the study analyses the impact on a cost model of the components of a VoIP network architecture, the usage factor of network elements, and the traffic volume generated by VoIP applications.

The issues described in the article can be used in elaborating a cost model for termination rates in VoIP networks. For the present study, no cost model was built, and therefore no quantitative estimations were made of the specific impact of every cost parameter on the termination rates.

The findings of this study can be used by policy makers, voice operators, and researchers.

Most studies of VoIP that are available in the literature address, on the one hand, the costs of corporate VoIP networks and, on the other, the regulation of VoIP services. This article, however, presents a comprehensive study of the most relevant features of VoIP network architectures that should be considered when determining regulated termination rates.