Search results

Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.

This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.

The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.

Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.

Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.

BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.

FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

This paper aims to present a design of a single power supply, low voltage (1.2) high performance operational amplifier using 0.13 μm technology whose characteristics are superior compared to the other designs available in the literature.

The authors set out to design an operational amplifier whose characteristics will be superior to the current available designs in the literature. Because of potential applications, a single 1.2 V supply was used. The layout was obtained using Microwind 0.13 μm technology. The design was tested using PSPICE Version 10.0. Various amplifier parameters were obtained and are compared with the other single supply, low voltage amplifiers available in the literature.

The presented amplifier has better characteristics such as open loop gain, power supply rejection ratio, common mode rejection ratio, etc.

Since, 0.13 μm, 1.2 V technology has become standard in digital VLSI design, there is a great need for high performance operational amplifiers that operate off of 1.2 V for mixed signal applications in such areas as mobile phones.

The presented amplifier has better characteristics compared to few 1.2 V supply voltage amplifiers available in the literature.

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

This paper aims to resolve the sizing issues of analog circuit design by using proposed metaheuristic optimization algorithm.

The hybridization of whale optimization algorithm and modified gray wolf optimization (WOA-mGWO) algorithm is proposed, and the same is applied for the automated design of analog circuits.

The proposed hybrid WOA-mGWO algorithm demonstrates better performance in terms of convergence rates and average fitness of the function after testing it with 23 classical benchmark functions. Moreover, a rigorous performance evaluation is done with 20 independent runs using Wilcoxon rank-sum test.

For evaluating the performance of the proposed algorithm, a conventional two-stage operational amplifier is considered. The aspect ratios calculated by simulating the algorithm in MATLAB are later used to design the operational amplifier in Cadence environment using 180nm CMOS standard process.

The hybrid WOA-mGWO algorithm is tailored to improve the exploration ability of the algorithm by combining the abilities of two metaheristic algorithms, i.e. whale optimization algorithm and modified gray wolf optimization algorithm. To build further credence and to prove its profound existence in the latest state of the art, a statistical study is also conducted over 20 independent runs, for the robustness of the proposed algorithm, resulting in best, mean and worst solutions for analog IC sizing problem. A comparison of the best solution with other significant sizing tools proving the efficiency of hybrid WOA-mGWO algorithm is also provided. Montecarlo simulation and corner analysis are also performed to validate the endurance of the design.

This paper will be presented in two parts. Part 1, after an introduction to thin film resistor technology, gives a review of thin films and other resistors, followed by designer's considerations when using resistors and networks. Part 2 will deal with assembly problems.

No‐clean flux printed board appraisal tests were conducted with all materials used in the production process. Metallic growths during environmental testing revealed that there was incompatibility between some materials used. Initial tests with two solder resists and several fluxes showed that one non solder resisted board, soldered using a synthetically activated (SA) flux, had surface insulation resistance (SIR) two decades higher than those using low solids flux (LSF) or other SAs. For boards with solder resist, the SIR of those soldered using LSFs was higher, however, than those using SA fluxes. SIR dependence on temperature and humidity was investigated. Results demonstrated that the dominant factor to determine the SIR of a no‐clean board was the characteristics of the board substrate finish. SIR changes with condensation were logged and found to be significant for solder resist finishes. Tests proved that reducing the contamination levels under and on top of the solder resist, by using hot de‐ionised water rinsing, enabled the calculated minimum SIR level to be achieved for spray fluxed boards and minimised the possibility of metallic growth. Visual examination proved to be at least as important as SIR testing. No‐clean processes were appraised using sequential environmental conditions with differing SIR pass levels. As a result of this appraisal a maximum ionic contamination level of 0·5 μg/cm2 NaCl equivalent and Dl water rinses, before and after solder resist added, will be introduced. Ionic contamination tests indicated that contamination levels reduced with elapsed time, probably due to ionic molecules locking more firmly into the board surface structure. A novel method for SIR measurements at any voltage, developed by the author, is described. It is hoped that this paper will further the understanding of no‐clean flux issues and highlight potential solutions and pitfalls.

This paper aims to present a comparison between three types of manufacturing techniques, namely, screen-printed, inkjet and gravure, using different types of inks, for the implementation of concentric ring electrodes which permit estimation of Laplacian potential on the body surface.

Flexible concentric ring electrodes not only present lower skin–electrode contact impedance and lower baseline wander than rigid electrodes but are also less sensitive to interference and motion artefacts. The above three techniques allow printing of conductive inks on flexible substrates, and with this work, the authors aim to study which is the best technique and ink to obtain the best electrode response.

From the results obtained regarding ink thickness, resistivity, electrode resistance and other performance parameters derived from electrocardiographic signal recording tests, it can be said that concentric electrodes using the screen-printing and inkjet techniques are suitable for non-invasive bioelectric signal acquisition.

The development of new types of inks and substrates for the electronics industry and the adaptation of new manufacturing techniques allow for an improvement in the development of electrodes and sensors.

This study aims to analyze the differences of electrocardiograph (ECG) characteristics for female drivers in calm and anxious states during driving.

The authors used various materials (e.g. visual materials, auditory materials and olfactory materials) to induce drivers’ mood states (calm and anxious), and then conducted the real driving experiments and driving simulations to collect driver’s ECG signal dynamic data. Physiological changes in ECG during the stimulus process were recorded using PSYLAB software. The paired T-test analysis was conducted to determine if there is a significant difference in driver’s ECG characteristics between calm and anxious states during driving.

The results show significant differences in the characteristic parameters of female driver’s ECG signals, including (average heart rate), (atrioventricular interval), (percentage of NN intervals > 50ms), (R wave average peak), (Root mean square of successive), (Q wave average peak) and ( S wave average peak), in time domain, frequency domain and waveform in emotional states of calmness and anxiety.

Findings of this work show that ECG can be used to identify driver’s anxious and calm states during driving. It can be used for the development of personalized driver assistance system and driver warning system.

Only a few attempts have been made on the influence of human emotions on physiological signals in the transportation field. Hence, there is a need for transport scholars to begin to identify driver’s ECG characteristics under different emotional states. This study will analyze the differences of ECG characteristics for female drivers in calm and anxious states during driving to provide a theoretical basis for developing the intelligent and connected vehicles.