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Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies.

The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results.

The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample.

The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system.

After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator.

The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm². The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology.

The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.

In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.

Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.

This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.

Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

The purpose of this paper is to present the design of a piezoelectric vibration energy generator with a power conditioning circuit to power a wireless sensor node. Frequency and voltage characterization of the piezoelectric energy harvester is performed. A single-stage AC–DC power converter that integrates the rectification and boosting circuit is designed, simulated and implemented in hardware.

The designed power conditioning circuit incorporates bridgeless boost rectification, a lithium ion battery as an energy storage unit and voltage regulation to extract maximum power from PZT-5H and to attain higher efficiency. The sensor node is modelled in active and sleep states on the basis of the power consumption. Dynamic modelling of the lithium ion battery with its state of charging and discharging is analysed.

The test result shows that the energy harvester produces a maximum power of 65.9 mW at the resonant frequency of 21.4 Hz. The designed circuit will operate even at a minimum input voltage of 0.5 V. The output from the harvester is rectified, boosted to a 7-V DC output and regulated to 3.3 V to the power C_Mote wireless sensor node. The conversion efficiency of the circuit is improved to 70.03 per cent with a reduced loss of 19.76 mW.

The performance of the energy harvester and the single-stage power conditioning circuit is analysed. Further, the design and implementation of the proposed circuit lead to an improved conversion efficiency of 70.03 per cent with a reduced loss of 19.76 mW. The vibration energy harvester is integrated with a power conditioning circuit to power a wireless sensor node C_Mote. The piezoelectric vibration energy harvester is implemented in real time to power C_Mote.

Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator.

The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module.

The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature.

A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.

This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.

As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.

Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

The purpose of this paper is to present the design and optimization of a comparator with two transistors.

The effect of back‐gate bias in MOSFET is analyzed and applied to a comparator circuit in a flash‐type A/D converter (ADC). The 4‐bit flash ADC is simply structured by change of comparator block based on CMOS latch with pMOSFET switch. The back‐gate bias on MOSFET changes the threshold voltage and provides for a CMOS inverter to shift the voltage transfer characteristics. In the new type comparator, the variation of turn‐on voltage is controlled within 0.1 V in 4‐bit ADC. The fabrication is done in a 0.35 μm single‐poly four‐metal process.

Layout simulation shows that INL is within 0.3 LSB and SNDR is 25.4 dB at input frequency of 20 KHz and sampling rate of 4 MS/s. The 0.26 × 0.43 mm 2 ADC dissipates 1.2 mW at supply voltage of 3.3 V.

A comparator which uses the effect of the back‐gate bias on MOSFET is applied to a flash ADC. The paper is of value in showing how the circuit of this comparator is quite simple compared with a conventional comparator based on a CMOS latch, which is adaptable for a low‐power analog circuit in future. The experimental output of the 4‐bit flash ADC shows a good agreement with a simulation. Power consumption 1.2 mW, INL 0.2 LSB, and SNDR 25 dB are obtained in the simulation study.