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In industrial distributed control environments for automation technology, Ethernet network based solutions are gaining prominence in the traditional fieldbus application areas with the promise of standardised solutions that can support real‐time operation to a resolution of less than 1 μm. However, there are no formal standards for a real‐time Industrial Ethernet. This paper looks at some of the emerging de facto solutions and describes a novel project where clusters of real‐time transducer networks are developed and the control is tightly synchronised using the IEEE 1588 clock synchronisation standard, realising a “Time‐triggered Ethernet” solution.

This paper uses a cognitive analytics management approach to analyze, understand and solve the problems facing the implementation of information systems and help management do the needed changes to enhance such a critical process; the emergency management system in the health industry is analyzed as a case study.

Cognitive analytics management (CAM) framework (Osman and Anouz, 2014) is used. Cognitive process: The right questions are asked to understand the behavior of every process and the flow of its corresponding data; critical data variables were identified, guidelines for identifying data sources were set. Analytics process: Techniques of data analytics were applied to the selected data sets, problems were identified in user–system interaction and in the system design. The analysis process helped the management in the management process to make right decisions for the right change.

Using the CAM framework, the analysis to the Lebanese Red Cross case study identified system user-behavior problems and also system design problems. It identified cases where distributed subsystems are vulnerable to time keeping errors and helped the management make knowledgeable decisions to overcome major obstacles by implementing several changes related to hardware design, software implementation, human resource training, operational and human-technology changes. CAM is a novel and feasible software engineering approach for handling system failures.

The paper uses CAM framework as an approach to overcome system failures and help management do the needed changes to enhance such a critical process. This work contributes to the software engineering literature by introducing CAM as a new agile methodology to be used when dealing with system failures. Furthermore, this study is an action research that validated the CAM theoretical framework in a health emergency context in Lebanon.

As the strategy of 5G new infrastructure is deployed and advanced, 5G-R becomes the primary technical system for future mobile communication of China’s railway. V2V communication is also an important application scenario of 5G communication systems on high-speed railways, so time synchronization between vehicles is critical for train control systems to be real-time and safe. How to improve the time synchronization performance in V2V communication is crucial to ensure the operational safety and efficiency of high-speed railways.

This paper proposed a time synchronization method based on model predictive control (MPC) for V2V communication. Firstly, a synchronous clock for V2V communication was modeled based on the fifth generation mobile communication-railway (5G-R) system. Secondly, an observation equation was introduced according to the phase and frequency offsets between synchronous clocks of two adjacent vehicles to construct an MPC-based space model of clock states of the adjacent vehicles. Finally, the optimal clock offset was solved through multistep prediction, rolling optimization and other control methods, and time synchronization in different V2V communication scenarios based on the 5G-R system was realized through negative feedback correction.

The results of simulation tests conducted with and without a repeater, respectively, show that the proposed method can realize time synchronization of V2V communication in both scenarios. Compared with other methods, the proposed method has faster convergence speed and higher synchronization precision regardless of whether there is a repeater or not.

This paper proposed an MPC-based time synchronization method for V2V communication under 5G-R. Through the construction of MPC controllers for clocks of adjacent vehicles, time synchronization was realized for V2V communication under 5G-R by using control means such as multistep prediction, rolling optimization, and feedback correction. In view of the problems of low synchronization precision and slow convergence speed caused by packet loss with existing synchronization methods, the observer equation was introduced to estimate the clock state of the adjacent vehicles in case of packet loss, which reduces the impact of clock error caused by packet loss in the synchronization process and improves the synchronization precision of V2V communication. The research results provide some theoretical references for V2V synchronous wireless communication under 5G-R technology.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

The purpose of this paper is to introduce several synchronization test methods of Network‐on‐Chip (NoC) at multi‐clock domains by digital logic circuits.

First, the authors gave the structure of NoC, the test methods for NoC in multi‐clock domains, including Built‐in Self Test (BIST) structure and the architecture of embedded core test. Then the authors approached four different synchronization structures: two‐level trigger, two kinds of lock methods, toggle and pulse synchronization methods. Based on the NoC work conditions, the authors built the experiment structures of different methods, and obtained the experiment results at high frequencies.

From the experiments at high frequency, it can be seen that the methods of toggle and the pulse methods are prone to failed synchronization. Therefore, the lock method is more appropriate for NoC under multiple clock domains.

In this paper, several synchronization test methods of NoC at multi‐clock domains are discussed and compared, and the best one determined.

A Bluetooth scatternet is a network topology that is formed by inter‐connecting piconets. A piconet is a starshaped ad‐hoc networking unit that can accommodate eight Bluetooth devices, a master and up to seven slaves. By designating certain piconet nodes as bridges, or gateways, we can interconnect piconets by forcing the bridge nodes to interleave their participation in multiple piconets. Bridge nodes form an auxiliary relay connection between adjacent piconet masters and are fundamental for establishing scatternets. In this paper we present a new fault‐tolerant approach to scatternet formation that is selfhealing and operates in a multi‐hop environment. Our Bluetooth Distributed Scatternet Formation Protocol (BTDSP) establishes a flat scatternet topology, allows incremental node arrival, and automatically heals scatternet partitions by re‐incorporating disconnected nodes. By maintaining neighbor associations in soft state, existing links can also be re‐established quickly upon disconnection due to intermittent wireless connectivity. By only using slave/slave bridges, the algorithm is resilient to both node failure and wireless interference. It also prevents time‐slot waste due to master/slave bridges being away from their piconets.

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

Ethernet continues to evolve as a viable fieldbus technology for industrial automation. This paper seeks to discuss the development of the Common Industrial Protocol (CIP) for Ethernet and standards with particular reference to time synchronisation, real time motion control and safety.

The CIP is introduced, with an overview of four network adaptations: CompoNet, DeviceNet, ControlNet, and EtherNet/IP. Developments in the EtherNet/IP implementation are discussed, along with key features. These include CIP Safety to meet the requirements for safety‐related control, CIP Sync for time synchronisation across CIP networks and CIP motion for real‐time closed loop motion control.

Standard, unmodified Ethernet will support time synchronisation, real time motion control and safety‐related applications with the CIP adaptation EtherNet/IP. The CIP enables complete integration of control with information, multiple CIP networks and internet technologies. CIP provides seamless communication from the plant floor throughout the enterprise, with a scalable and coherent architecture, incorporating functionality, such as safety, time synchronisation and motion control, hitherto only available with specialised or incompatible networks.

The implementations of CIP Sync, CIP Motion and CIP Safety and the corresponding standards provide functionality and flexibility not available from disparate specialist networks. The ability to fully integrate internet technologies and safety, synchronisation, motion and safety together is a distinguishing feature. Industrial Ethernet technologies vary in the ability to integrate to the same level of functionality and offer similar flexibility.

The development of CIP technology and the use of open standards are described. The opportunity to use the combination of an established automation protocol and standard, unmodified Ethernet provides potential cost benefits, flexibility, and innovative solutions, whilst providing integration, performance and cost advantages.

RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system.

After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator.

The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm². The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology.

The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.