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Multistage amplifiers require a reliable frequency compensation solution to remain stable in a closed-loop configuration. A frequency compensation scheme creates an inner negative feedback loop amongst different amplifying stages and shapes the frequency response such that an unconditionally stable single-pole amplifier results for closed-loop operation. The frequency compensation loop is thus responsible for the placement of the poles and zeros and the final stability of multistage amplifiers. An amplifier incorporating a sophisticated frequency compensation network cannot be, however, analyzed in the presence of a complex ac feedback loop. The purpose of this study is to provide a reliable model for the compensation loop of multistage amplifiers at the higher frequencies.

In this paper, the major part of the amplifier, including a two-port network comprising the compensation network, is characterized using a reliable feedback model.

The model integrates all the frequency-dependent components of the frequency compensation network, and it can evaluate the nondominant real or complex poles of an amplifier.

The reliability of the proposed model is verified through analysis of the frequency response of the amplifiers and by comparing the analytic results with the simulation results in standard CMOS process.

This paper aims to present a design of a single power supply, low voltage (1.2) high performance operational amplifier using 0.13 μm technology whose characteristics are superior compared to the other designs available in the literature.

The authors set out to design an operational amplifier whose characteristics will be superior to the current available designs in the literature. Because of potential applications, a single 1.2 V supply was used. The layout was obtained using Microwind 0.13 μm technology. The design was tested using PSPICE Version 10.0. Various amplifier parameters were obtained and are compared with the other single supply, low voltage amplifiers available in the literature.

The presented amplifier has better characteristics such as open loop gain, power supply rejection ratio, common mode rejection ratio, etc.

Since, 0.13 μm, 1.2 V technology has become standard in digital VLSI design, there is a great need for high performance operational amplifiers that operate off of 1.2 V for mixed signal applications in such areas as mobile phones.

The presented amplifier has better characteristics compared to few 1.2 V supply voltage amplifiers available in the literature.

The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.

To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.

Measurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.

The strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.

The purpose of this study is to discuss the effect of hybrid cascode compensation with quality factor (Q-factor) control module for the three-stage amplifiers driving ultra-large load capacitors. Compared to the present frequency compensation solutions, it extends the amplifier bandwidth by establishing an extra AC feedback pathway besides the primary pathway through the Miller capacitor, increasing the loop gain at the gain–bandwidth product (GBW) frequency by pushing to the higher frequencies the nondominant poles.

A Q-factor control block is used to improve the damping factor of the compensation loop with no power or area overhead, thereby reducing the frequency peaking and the undesired oscillation in the time response for small load capacitors. The Q-factor control module is realized by a tiny-size on-chip capacitor, and provides an extra feedback loop to feed the damping current back to the input stage. A left-half-plane (LHP) zero is also introduced to further improve the stability.

A prototype of the proposed amplifier is simulated in 180-nm CMOS with a quiescent current of 24-µA from 1.80-V voltage supply. It achieves a 3.98-MHz gain–bandwidth product for 500-pF load capacitor, while the overall compensation capacitor is limited to 0.5-pF and the DC gain is extended beyond 100-dB.

The proposed amplifier is absolutely stable for the load capacitors ranging between 80-pF and 100-nF.

Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications.

A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks.

By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm² and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz.

The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).

The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (g_m3) to be canceled with the main PA’s fixed negative g_m3. The g_m3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.

For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.

In this study, a novel cascaded g_m3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

The purpose of the paper is to report an emulation configuration of a three pinch-off memristor (TPM), whose transient characteristics consist three cross-over points on the voltage-current plane, which is dissimilar to a conventional memristor. These characteristics can be very useful in memristor-based multi-bit memory devices and hyperchaotic oscillators.

The work describes the Mathematical framework for TPM and a circuit emulator based on the derived conditions. The configuration is based on five operational transconductance amplifier (OTAs) and four grounded passive elements. After which, we have verified its operation using personal simulation program with integrated circuit emphasis simulation environment. Finally, the implementation of OTA-based TPM using commercial integrated circuit (IC) LM13700 has also been presented.

It has been shown that a flux-dependent memductance expression of cubic order can show three intersections on the VI contour under certain parameter related constraints. Moreover, the OTA-based emulator reported in the work is very compact in nature because of the no use of external multiplier IC/circuitry, which has been popular in previous emulators.

For the first time, a multiple cross-over memristor emulator has been reported which can operate under practical operating conditions such as at practical operating frequencies and sinusoidal excitation.

The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.

An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm².

Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.

The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

This study aims to present two stage pseudomorphic high electron mobility transistor-based low noise amplifier (LNA) designed using low temperature co-fire ceramic (LTCC) technique for ultra-high frequency (UHF) band. The LNA operates in the frequency range of (400∼500) MHz which is suitable for wireless communication applications.

This LNA uses resistive capacitive (RC) feedback in the first stage to have wide bandwidth and interstage network for gain enhancement. By using external RC feedback, stability is improved and noise matching in the input stage is isolated by decoupling inductor. The excellent performance parameters including gain, noise figure (NF), wideband and linearity are attained without affecting the power consumption, compactness and cost of the proposed design.

Simulation is carried out using advanced design software and the result shows that gain of 33.7 dB, NF 0.416 dB and 1 dB compression point (P_1dB) of 18.59 dBm are achieved with a supply voltage of 2.5 V. The return loss of input and output are −19.3 dB and −10.5 dB, respectively. From the above aforementioned parameters, it is confirmed that the proposed LNA is a promising candidate for receivers where high gain and very low NF are always demandable with good linearity for applications operating in the UHF band.

The innovation of the proposed LNA is that the concurrent attainment of high gain, low NF, wideband, optimum input matching, good stability by RC feedback and interstage network using LTCC technique to achieve robustness, low cost and compactness to prove the applicability of design for wireless applications.

The purpose of the paper is to quantify the impact of the non-uniform flow generated by the upstream stator on the generation and convection of the tip leakage flow (TLF) structures in the passages of the rotor blades in a low-speed axial fan.

A full three dimensional (3D)-viscous unsteady Reynolds-averaged Navier-stokes (RANS) (URANS) simulation of the flow within a periodic domain of the axial stage has been performed at three different flow rate coefficients (φ = 0.38, 0.32, 0.27) using ReNormalization Group k-ε turbulence modelling. A typical tip clearance of 2.3 per cent of the blade span has been modelled on a reduced domain comprising a three-vaned stator and a two-bladed rotor with circumferential periodicity. A non-conformal grid with hybrid meshing, locally refined O-meshes on both blades and vanes walls with (100 × 25 × 80) elements, a 15-node meshed tip gap and circumferential interfaces for sliding mesh computations were also implemented. The unsteady motion of the rotor has been covered with 60 time steps per blade event. The simulations were validated with experimental measurements of the static pressure in the shroud of the blade tip region.

It has been observed that both TLF and intensities of the tip leakage vortex (TLV) are significantly influenced by upstream stator wakes, especially at nominal and partial load conditions. In particular, the leakage flow, which represents 12.4 per cent and 11.3 per cent of the working flow rate, respectively, has shown a clear periodic fluctuation clocked with the vane passing period in the relative domain. The periodic fluctuation of the TLF is in the range of 2.8-3.4 per cent of the mean value. In addition, the trajectory of the tip vortex is also notably perturbed, with root-mean squared fluctuations reaching up to 18 per cent and 6 per cent in the regions of maximum interaction at 50 per cent and 25 per cent of the blade chord for nominal and partial load conditions, respectively. On the contrary, the massive flow separation observed in the tip region of the blades for near-stall conditions prevents the formation of TLV structures and neglects any further interaction with the upstream vanes.

Despite the increasing use of large eddy simulation modelling in turbomachinery environments, which requires extremely high computational costs, URANS modelling is still revealed as a useful technique to describe highly complex viscous mechanisms in 3D swirl flows, such as unsteady tip flow structures, with reasonable accuracy.

The paper presents a validated numerical model that simulates the unsteady response of the TLF to upstream perturbations in an axial fan stage. It also provides levels of instabilities in the TLV derived from the deterministic non-uniformities associated to the vane wakes.