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A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz.

This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications.

The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping.

This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

Describes the improvements that smart sensors will bring to electronic measurement and control systems, and the advantages of using integrated sensors. Outlines the problems encountered when designing integrating electronics for use on a smart sensor chip and lists the major functions that smart sensors must perform. Concludes that the solution to many real life sensor problems will only be found when a well designed “care‐free” intelligent sensor can be produced and continues that the way to realize this concept is to combine a sensor device with a number of micro‐electronic components into a single sensor package.

As technology advances the demand for an analog-to digital converter has increased, as every application demands a converter as per its parameters. Currently, work is done on improvement of data converters at three levels of design – architectural, circuit and physical level. This paper aims to review the work done in the field of analog-to-digital converters (ADCs) at architectural and circuit level and discusses the achievements in this field. Furthermore, a new architecture is proposed, which works at higher resolution and provides optimum design parameters at low power consumption.

A hybrid architecture combining the features of synthetic approximation register and sigma-delta ADC is presented. The validity of the proposed design at architectural level is verified using MATLAB SIMULINK simulations.

The design simulation was tested for a sinusoidal wave of 1 V at the test frequency of 60 Hz. The design consumes least power, and is found to yield an error of the order less than 10–3 V, thus providing highly accurate digital output.

The design is applicable in many applications including biomedical systems, Internet-of-Things and earthquake engineering. This architecture can be further optimized to obtain better performance parameters.

The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies.

The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results.

The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample.

The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

The purpose of this paper is to introduce the theoretical basis of N-order spectral spreading-compressing (SSC) frequency shift interference algorithm and expand it to active cancellation. An active cancellation simulation and verification system based on N-order SSC algorithm is established and carried out; simultaneously, the absorbing material coating stealth simulation of two kinds of thickness is carried out to compare the stealth effect with active cancellation system.

The active cancellation method based on N-order SSC algorithm is proposed based on theoretical formula derivation; the active cancellation simulation and verification system is established in MATLAB/Simulink. The full-size model is built by CATIA and meshed by hypermesh. The omnidirectional radar cross section (RCS) is calculated in cadFEKO, and the results are analyzed in postFEKO.

The simulations are implemented on a stealth fighter, and results show that after active cancellation, the peak of spectrum analyzer has reduced in all azimuths, the omnidirectional RCS has also decreased and the detection probability of almost all azimuths has dropped under 50 per cent. The absorbing material coating stealth simulations of two kinds of thickness are carried out, and results show that the stealth effect of active cancellation is much better than absorbing material coating.

An active cancellation system based on SSC algorithm is proposed in this paper, and the effect of active cancellation is verified and compared with that of absorbing materials. A new method for the current active stealth is provided in this paper.

Active cancellation simulation and verification system is established. RCS calculation module, signal-to-noise-ratio (SNR) calculation module and detection probability module are built to verify the effect of active cancellation system. Simultaneously, the absorbing material coating stealth simulation is carried out, and the stealth effect of absorbing material coating and active cancellation are compared and analyzed.

This paper concerns with the measurement uncertainty estimation in the analog‐to‐digital conversion‐based instruments. By using an ad hoc developed software tool, the Monte Carlo method is applied in order to assess the uncertainties associated with the measurement results, overcoming the possible inapplicability of the pure theoretical approach prescribed in the ISO – “Guide to the Expression of Uncertainty in Measurement”. By implementing the software tool in the measurement instruments, the proposed approach can be utilized in order to make the instrument itself able to auto‐estimate the measurement uncertainties.

Wireless sensor networks (WSN), as a solution for buried water pipe monitoring, face a new set of challenges compared to traditional application for above-ground infrastructure monitoring. One of the main challenges for underground WSN deployment is the limited range (less than 3 m) at which reliable wireless underground communication can be achieved using radio signal propagation through the soil. To overcome this challenge, the purpose of this paper is to investigate a new approach for wireless underground communication using acoustic signal propagation along a buried water pipe.

An acoustic communication system was developed based on the requirements of low cost (tens of pounds at most), low power supply capacity (in the order of 1 W-h) and miniature (centimetre scale) size for a wireless communication node. The developed system was further tested along a buried steel pipe in poorly graded SAND and a buried medium density polyethylene (MDPE) pipe in well graded SAND.

With predicted acoustic attenuation of 1.3 dB/m and 2.1 dB/m along the buried steel and MDPE pipes, respectively, reliable acoustic communication is possible up to 17 m for the buried steel pipe and 11 m for the buried MDPE pipe.

Although an important first step, more research is needed to validate the acoustic communication system along a wider water distribution pipe network.

This paper shows the possibility of achieving reliable wireless underground communication along a buried water pipe (especially non-metallic material ones) using low-frequency acoustic propagation along the pipe wall.

This paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.

Virtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.

The proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.

Virtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.

An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm².

Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.

The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.