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1 – 10 of 20Mohammad Sadegh Mirzajani Darestani, Mohammad Bagher Tavakoli and Parviz Amiri
The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.
Abstract
Purpose
The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.
Design/methodology/approach
To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.
Findings
Measurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.
Originality/value
The strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.
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Yanfeng Fang and Yijiang Zhang
This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the…
Abstract
Purpose
This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems.
Design/methodology/approach
The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation.
Findings
The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm2 (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply.
Originality/value
In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.
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Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Yusman Yusof and Narendra Kumar
The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of…
Abstract
Purpose
The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).
Design/methodology/approach
The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.
Findings
For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.
Originality/value
In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.
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Lin-sheng Liu, Qian Lin, Hai-feng Wu, Yi-Jun Chen and Liu-Lin Hu
The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.
Abstract
Purpose
The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.
Design/methodology/approach
To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.
Findings
Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm2.
Originality/value
To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.
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Premmilaah Gunasegaran, Jagadheswaran Rajendran, Selvakumar Mariappan, Yusman Mohd Yusof, Zulfiqar Ali Abdul Aziz and Narendra Kumar
The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while…
Abstract
Purpose
The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).
Design/methodology/approach
The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.
Findings
With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.
Practical implications
The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.
Originality/value
The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.
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Min Liu, Panpan Xu, Jincan Zhang, Bo Liu and Liwen Zhang
Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential…
Abstract
Purpose
Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications.
Design/methodology/approach
A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks.
Findings
By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz.
Originality/value
The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.
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Yusuke Ikemoto, Shingo Suzuki, Hiroyuki Okamoto, Hiroki Murakami, Hajime Asama, Soichiro Morishita, Taketoshi Mishima, Xin Lin and Hideo Itoh
The purpose of this paper is to describe the development of a contactless and batteryless loading sensor system that can measure the internal loading of an object structure…
Abstract
Purpose
The purpose of this paper is to describe the development of a contactless and batteryless loading sensor system that can measure the internal loading of an object structure through several covering materials for structural health monitoring.
Design/methodology/approach
The paper proposed an architecture by which two radio frequency identification (RFID) tags are used in the system. It has been difficult to realize sensing by RFID because of the low power supply. To solve the power supply problem, a method using functional distribution of RFID tags of two kinds of RFID for communication and power supply was proposed. One RFID tag is specialized as a power supply for communication of strain loading information through A/D conversion. Another is specialized to supply power for driving the strain gauges bridge circuit.
Findings
By using developed system, the measurement of the structural internal loading with 20.0 mm depth was possible through covering materials such as concrete, but also plaster board, flexible boards, silicate calcium board, blockboard, and polystyrene with a resolution performance from 10 × 10−6 to 40 × 10−6.
Originality/value
A sensor system was developed using passive RFID, which enables measurement of load‐deformation information inside a structural object. Moreover, the inexpensive wireless, batteryless devices used in this system require little maintenance, and applications for the user interface are also included in the developed system for uniform management of structural health monitoring. The developed system was evaluated in an actual situation using not only concrete but also other materials as covering materials on a structural object.
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Sudheer Gupta, Stefanie Beninger and Jai Ganesh
This paper aims to provide a detailed analysis of the key capabilities needed for social enterprises to succeed in the context of extreme poverty. Facilitating growth and…
Abstract
Purpose
This paper aims to provide a detailed analysis of the key capabilities needed for social enterprises to succeed in the context of extreme poverty. Facilitating growth and alleviating poverty in the world’s most impoverished regions requires introducing innovative solutions to achieve social impact while generating financial returns.
Design/methodology/approach
This paper studies two social enterprises operating in Africa. Semi-structured interviewers were conducted with co-founders of the organizations. The transcribed interviews were analyzed through an open coding process, iterated to overarching categories, and compared between the organizations using a grounded theory approach. Secondary archival data and respondent validation were used to triangulate these findings.
Findings
This paper proposes a model that highlights five key capabilities social enterprises need to tackle complex societal challenges while overcoming resource constraints and institutional voids. The processes followed to develop and deploy these capabilities are delineated, and the necessity of hybrid mechanisms that blend non-profit and private-sector approaches is shown as a key enabler for social enterprises to meet their dual objectives.
Research limitations/implications
This research is limited to two cases studies from two different industries in Africa. Future research would refine and extend the proposed model to increase generalizability.
Originality/value
This paper addresses a gap in the literature on understanding innovation and entrepreneurship in Africa, and it proposes a model for innovation derived from data. This paper also offers insights to the growing community of social entrepreneurs looking to develop sustainable solutions to societal challenges.
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The purpose of this paper is to define the process of analog circuit optimization on the basis of the control theory application. This approach produces many different strategies…
Abstract
Purpose
The purpose of this paper is to define the process of analog circuit optimization on the basis of the control theory application. This approach produces many different strategies of optimization and determines the problem of searching of the best strategy in sense of minimal computer time. The determining of the best strategy of optimization and a searching of possible structure of this strategy with a minimal computer time is a principal aim of this work.
Design/methodology/approach
Different kinds of strategies for circuit optimization have been evaluated from the point of view of operations’ number. The generalized methodology for the optimization of analog circuit was formulated by means of the optimum control theory. The main equations for this methodology were elaborated. These equations include the special control functions that are introduced artificially. This approach generalizes the problem and generates an infinite number of different strategies of optimization. A problem of construction of the best algorithm of optimization is defined as a typical problem of the control theory. Numerical results show the possibility of application of this approach for optimization of electronic circuits and demonstrate the efficiency and perspective of the proposed methodology.
Findings
Examples show that the better optimization strategies that are appeared in limits of developed approach have a significant time gain with respect to the traditional strategy. The time gain increases when the size and the complexity of the optimized circuit are increasing. An additional acceleration effect was used to improve the properties of presented optimization process.
Originality/value
The obtained results show the perspectives of new approach for circuit optimization. A large set of various strategies of circuit optimization serves as a basis for searching the better strategies with a minimum computer time. The gain in processor time for the best strategy reaches till several thousands in comparison with traditional approach.
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