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Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system.

After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator.

The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm². The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology.

The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.

This study aims to provide an objective analysis of the state-of-the-art and intellectual development of publications related to event study methodology in business research.

The sample includes 1,219 papers related to event study methodology, covering all business disciplines and spanning 34 years from 1983 to 2016.

Through three stages of primary analysis, namely, initial sample, citation and co-citation analyses, the authors identified the publication trends, supplementary techniques, influential publications and intellectual clusters in the area of event study methodology in business.

The findings serve as a benchmark for the extensive literature related to event study methodology in business and may facilitate the transference of the amassed useful techniques among disciplines and the identification of future research directions.

The current study represents as a pioneering effort to review event study-related publications using bibliometric analysis.

The authors propose novel tests for the detection of Markov switching deviations from forecast rationality. Existing forecast rationality tests either focus on constant deviations from forecast rationality over the full sample or are constructed to detect smooth deviations based on non-parametric techniques. In contrast, the proposed tests are parametric and have an advantage in detecting abrupt departures from unbiasedness and efficiency, which the authors demonstrate with Monte Carlo simulations. Using the proposed tests, the authors investigate whether Blue Chip Financial Forecasts (BCFF) for the Federal Funds Rate (FFR) are unbiased. The tests find evidence of a state-dependent bias: forecasters tend to systematically overpredict interest rates during periods of monetary easing, while the forecasts are unbiased otherwise. The authors show that a similar state-dependent bias is also present in market-based forecasts of interest rates, but not in the forecasts of real GDP growth and GDP deflator-based inflation. The results emphasize the special role played by monetary policy in shaping interest rate expectations above and beyond macroeconomic fundamentals.

The study aims to examine the relationship among economic policy uncertainty (EPU), geopolitical-risks (GPR), the interaction (EPGR) of EPU and GPR and the returns of gold, silver, platinum, palladium and rhodium using monthly data from January (1997) to May (2021).

The paper employs the Markov-switching and the novel Shi et al. (2020) bootstrap time-varying Granger-causality approach.

Though the Markov-switching shows variation in the responses of precious metals to EPU, GPR and EPGR across low and high states, the paper observes the safe-haven potential of the precious metals in the high regime while the hedging potency is also evident in the results. To further substantiate the safe-haven and hedging properties, the time-varying Granger-causality shows the causal effect of EPU on all the selected precious metal returns coinciding with global events. While the authors show that GPR Granger causes platinum, palladium and rhodium consistently under the rolling/recursive-evolving tests, the authors cannot find the causal effect of GPR on gold and silver returns across the algorithms. The paper also observes persistence in the causal effect of EPGR on palladium and platinum across all the algorithms, while gold and rhodium only show consistency in the responses under the rolling- and recursive-evolving algorithms given the conditions of homoscedasticity and heteroscedasticity.

The authors' results are essential to investors and policymakers since both typically leverage the hedging and safe-haven characteristics of precious metals to obviate downside risks during highly uncertain periods.

The authors' techniques allow examining the hedging and safe-haven properties of precious metals across regimes and date-stamp critical periods of causation inherent in the relationship.

The main purpose of this paper is to select appropriate voltage vectors in the switching techniques and, by selecting the proper voltage vectors, be able to achieve a DC link with the same outputs and a symmetric multi-level inverter.

The proposed structure, a two-stage DC–AC symmetric multi-level inverter with modified Model Predictive Control (MMPC) method, is presented for Photovoltaic (PV) applications. The voltage of DC-link capacitors of the boost converter is controlled by MMPC control method to select appropriate switching vectors for the multi-level inverter. The proposed structure is provided for single-phase power system, which increases 65 V input voltage to 220 V/50 Hz output voltage, with 400 V DC link. Simulation results of proposed structure with MMPC method are carried out by PSCAD/EMTDC software.

Based on the proposed structure and control method, total harmonic distortion (THD) reduces, which leads to lower power losses and higher circuit reliability. In addition, reducing the number of active switches in current path causes to lower voltage stress on the switches, lower PV leakage current and higher overall efficiency.

In the proposed structure, a new control method is presented that can make a symmetric five-level voltage with lower THD by selecting proper switching for PV applications.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

The purpose of this paper is to present analysis of the feedback predictive encoder-based analog-to-digital converter (ADC).

The use of feedback predictive encoder-based ADCs presents an alternative to the traditional two-stage pipeline ADC by replacing the input estimate producing first stage of the pipeline with a predictive loop that also produces an estimate of the input signal.

The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical usable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum usable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimization of the power consumption.

A practical switched capacitor implementation of the predictive encoder-based ADC is proposed. The power consumption of key circuit blocks is investigated.

This paper presents a methodology to optimize the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimization of power consumption based on the allocation of time between the gain stage and the successive approximation register ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.

The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.

An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm².

Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.

The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.