Search results

The evolution of civil aircraft technology has been characterised by a drive towards three goals: the improvement of safety, the increase of operational reliability and the reduction in the actual cost of flying from A to B. This evolution has now been oversha‐dowed by another evolution, more widespread in its application, that of micro‐circuit technology. Avionics has at last come of age with the introduction of micro‐compters into all aspects of the control of aircraft where they provide consistent high‐speed decision‐making with the facility for self‐monitoring. In addition, the overall systems employing the micro‐computers represents a saving in weight, yet bring with them greatly enhanced flexibility of operation. The aircraft due to enter service in the next few years are likely to provide supreme examples of this burgeoning of avionics in providing extensive improvements in passenger comfort and safety together with optimisation of the economics of flying.

The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies.

The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results.

The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample.

The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

The demand for higher bandwidth has resulted in the development of mm-wave phased array systems. This paper aims to explore a technique that could be used to feed the individual antennas in a mm-wave phased array system with the appropriate phase shifted signal to achieve the required directivity. It presents differential Colpitts oscillators at 5 and 60 GHz that can provide differential output signals to the quadrature signal generators in the proposed phase shifter system.

The phase shifter system comprises a differential Colpitts voltage controlled oscillator (VCO) and utilizes the vector-sum technique to generate the phase shifted signal. The differential VCO is connected in the common-collector configuration for the 5-GHz VCO, and is extended using a cascode transistor for the 60-GHz VCO for better stability at mm-wave. The vector sum is achieved using a variable gain amplifier (VGA) that combines the in-phase and quadrature phase signal, generated from oscillator output using hybrid Lange couplers. The devices were fabricated using IBM 130-nm SiGe BiCMOS process, and simulations were performed with a process design kit provided by the foundry.

The measured results of the 5-GHz and 60-GHz VCOs indicate that differential Colpitts VCO could generate oscillator output with good phase noise performance. The simulation results of the phase shifter system indicate that the generation of signals with phases from 0° to 360° in steps of 22.5° was achieved using the proposed approach. A Gilbert mixer topology was used for the VGA and the linearity was improved by a pre-distortion circuit implemented using an inverse tanh cell.

The measurement results indicate that differential Colpitts oscillator in common-collector configuration could be used to generate differential VCO signals for the vector-sum phase shifter. The simulation results of the proposed phase shifter system at mm-wave show that the phase shift could be realised at a total power consumption of 200 mW.

This work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V) CMOS technology node. Improved sensor accuracy contributes to efficiency in switched supplies by reducing measurement errors when it is integrated with closed-loop control.

Integrated current-sensing methods were investigated and CMOS solutions were prioritized. These solutions were implemented and characterized in the desired process and shortcomings were identified. A theoretical analysis accompanied by simulated tests was used to refine improvements which were prototyped. The current sensor prototypes were fabricated and tested.

Measured and simulated results are presented which show improved linearity in current sensor outputs. Techniques borrowed from analog amplifier design can be used to improve the dynamic range and linearity of current-steered CMOS pairs for measuring current. A current sensor with a gain of 5 V/A operating in a 10 MHz switch mode supply environment is demonstrated.

This paper proposes an alternative approach to creating suitable bias conditions for linearity in a SenseFET topology. The proposed method is compact and architecturally simple in comparison to other techniques.

The purpose of this paper is to develop a model of the inductive link for implantable systems. The model is suitable for a cochlear implant in which a lateral misalignment and distance coil can be up to 16 mm.

The description of the generation of implantable systems' high‐power, such as a cochlear implant, are powered by transcutaneous inductive power links formed by two coils: the first is a printed spiral coil used in the receiver device and the second is a solenoid coil used in the emitter device. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. The authors have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi‐empirical models to predict parasitic components. The power amplifier itself is a class‐E amplifier optimized in both output voltage and efficiency, and bears an excellent tolerance to misalignments.

Two Spice‐based electrical models of the coils are achieved. The technique employed during the work is based on polynomial interpolation of the mutual inductance in which coil misalignments are considered as variables. On the other hand, a voltage regulator is studied and simulated by Cadence Analog Artist in the AMS 0.35 μm CMOS technology.

This paper provides a novel and useful method for transmitting power for an implantable system via an inductive link. The procedure of the authors' design is achieved at 10 MHz and the power transmission efficiency is 35 percent, whatever the longitudinal misalignment (up to 16 mm) between both coils.

This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD).

The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column driver IC and clock controller are integrated in 0.18 μm CMOS technology with 1-poly and 4-metal process.

The post-layout simulation shows that the proposed column driver circuit for LCD driver IC significantly reduces the peak switching current, and it results in the reduction of EMI noise level by more than 15 dB. It is obtained with 20 segmented operations in data latch at 40 MHz frequency.

The advantage of the cascode current source is that it can provide a well-controlled bias current with an accurate current transfer ratio. To reduce the EMI noise in LCD driver circuit, the cascode current source is properly located for the DC bias block in the level shifter. The application is rarely done by others, and a significant EMI noise reduction is found. The well-controlled current source provides a high performance switching in the level shifter.

Modern wireless communications need novel microwave components that can be effectively used for high data rate and low-power applications. The operating environment decides the severity of the noise coupled to the transceiver system from the ambient environment. In a deep fading environment, narrowband systems fail where the wideband systems come for rescue. Thus, the microwave components are ought to switch between the narrowband and wideband states. This paper aims to study the design of a bandpass filter to meet the requirements by appropriately switching between the dual narrowband frequencies and single ultra-wideband frequency band.

The design and implementation of a compact microwave filter with reconfigurable bandwidth characteristics are presented in this paper. The proposed filter is constructed using a hexagonal ring with shorted perturbation along one corner. The filter is capacitively coupled to the external excitation source. External stubs are connected to the corners of the hexagonal resonator to obtain dual passband characteristics centred at 2.1 and 4.5 GHz. The external stubs are configured to achieve bandwidth reconfigurable characteristics. PIN diodes are used with a suitable biasing network to obtain reconfiguration. In the reconfigured state, the proposed two-port filter offers a continuous bandwidth from 2.1 to 5.9 GHz. The roll-off rate along the band edges is improved by increasing the order of the filter.

The proposed filter operates in two states. In state 1, the filter operates with dual frequencies centred around 2 and 4.5 GHz with insertion loss less than <1 dB and return loss greater than 13 dB with a peak return loss of 21 and 31 dB at 2.1 and 2.15 GHz, respectively. In state 2, the filter operates from 2.1 to 5.9 GHz with insertion loss less than 1 dB and return loss greater than 12 dB. The filter exhibits four-pole characteristics with a peak return loss greater than 22 dB. Thus, the fractional bandwidth of the proposed filter is 17% and 16% in state 1, whereas the fractional bandwidth is 95% in state 2.

The proposed filter is the first of its kind to simultaneously offer miniaturization and bandwidth reconfiguration. The proposed second-order filter has two-pole characteristics in the narrowband state, whereas four-pole characteristics are realized in the wideband state. The growing interest in 4G and 5G wireless communications makes the proposed filter a suitable candidate for operation in the rich scattering environment.

Nanowires, nanostructures with the diameter of the order of a nanometer, have recently attracted as gas sensors because of their interesting properties such as high sensitivity, fast response and high selectivity and stability. Among the different types of gas sensors, metallic nanowires used in high frequency applications because of their long mean free path that make the conduction ballistic.

This paper presents the results of simulations to find the effects of adsorbing some molecules by silver Ag nanowires. The mechanisms of the simulated gas sensor are implemented in the Atomistix Toolkit 13.2 (ATK 13.2).

The simulation results show high sensitivity of silver nanowires in adjacent with water and ethane. The resistance of the simulated nanowire increased to about 3.65 kΩ for ethane and 4.95 kΩ for water molecules. This result shows that the sensitivity of a silver nanowire is about triple for the case of adsorbing water in comparison to the adsorption of ethane molecules.

This paper presents a simulation study on silver nanowires and compares their sensitivities in adjacent with water and ethane molecules.

The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz.

A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of −33 dBc close to the 1 dB gain compression point.

With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than −18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of −33 dBc is achieved at maximum linear output power of 31 dBm.

The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits.

In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

The purpose of this paper is to demonstrate the non-destructive methods for detection and localization of interconnection structure discontinuities based on the signal analysis in the frequency and time domain.

The paper deals with the discontinuity characterization of interconnection structures created on substrates used for electronics, and methods for their detection and localization, based on the frequency analysis of transmitted signals. Used analyses are based on the theoretical approach for the solution of discontinuity electrical parameters and are the base for diagnostic methods of discontinuity identification.

The measurement results of reflection parameters, frequency spectrums of transmitted signals and characteristic impedance values are presented on test samples containing multiple line cracks and their width reduction.

Obtained results can be used practically, not only for the detection of transmission lines discontinuities on printed circuit boards but also in other applications, such as the quality assessment of bonded joints.

Developed methods allow the quick identification and localization of particular discontinuities without the destruction of tested devices.