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Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator.

The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module.

The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature.

A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

This paper aims to implement a novel design of approximate comparator which can be suitable for image processing applications.

Here, the N-bit approximate comparator is implemented by taking reference of N as 2-, 4- and 8-bit. The design analyses the fractional change in error to bit in several bit formats. The final implementation of approximate comparator design application compares the structural similarity index, colour test and extraction of an image to the results.

The novel approximate comparator was designed using 2-, 4- and 8-bit to explore N-bit comparator expressions. The implementation, computations, evaluation of errors, applications and the design constraints were executed using Python and Synopsys, respectively. The computations, evaluation of errors, applications and the design constraints were executed using Python and Synopsys, respectively.

This paper presents the N-bit accurate and approximate comparator which is novel over the existing design of comparators.

Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA.

As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator.

Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects.

A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.

The purpose of this paper is to present the design and optimization of a comparator with two transistors.

The effect of back‐gate bias in MOSFET is analyzed and applied to a comparator circuit in a flash‐type A/D converter (ADC). The 4‐bit flash ADC is simply structured by change of comparator block based on CMOS latch with pMOSFET switch. The back‐gate bias on MOSFET changes the threshold voltage and provides for a CMOS inverter to shift the voltage transfer characteristics. In the new type comparator, the variation of turn‐on voltage is controlled within 0.1 V in 4‐bit ADC. The fabrication is done in a 0.35 μm single‐poly four‐metal process.

Layout simulation shows that INL is within 0.3 LSB and SNDR is 25.4 dB at input frequency of 20 KHz and sampling rate of 4 MS/s. The 0.26 × 0.43 mm 2 ADC dissipates 1.2 mW at supply voltage of 3.3 V.

A comparator which uses the effect of the back‐gate bias on MOSFET is applied to a flash ADC. The paper is of value in showing how the circuit of this comparator is quite simple compared with a conventional comparator based on a CMOS latch, which is adaptable for a low‐power analog circuit in future. The experimental output of the 4‐bit flash ADC shows a good agreement with a simulation. Power consumption 1.2 mW, INL 0.2 LSB, and SNDR 25 dB are obtained in the simulation study.

The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies.

The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results.

The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample.

The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

This paper aims to introduce a new novel microstrip monopulse comparator system to reduce the spurious radiation from the comparator and the feed network for achieving better radiation performance.

Two substrate layers have been used for the microstrip monopulse comparator system. The feed network and the comparator circuits are on the first substrate layer and the microstrip array antenna is on the second layer. The elements of the array antenna are novel square four-sided narrow rectangular slot antennas built on a conducting plane. A commercially available computational software, CST microwave studio, has been used for the analysis of the system.

Two substrate layers have been used for the microstrip monopulse comparator system. The feed network and the comparator circuits are on the first substrate layer and the microstrip array antenna is on the second layer. The elements of the array antenna are novel square four-sided narrow rectangular slot antennas built on a conducting plane. A commercially available computational software, CST microwave studio, has been used for the analysis of the system.

The system is proposed for tracking moving targets.

Novel slot radiators are introduced as radiating elements in this paper. The antenna arrangement shields the comparator and the feed network circuits, reducing the spurious radiation significantly.

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

This paper aims to explore the possibilities in using such national, statutory data sets for evaluating change and the challenges of understanding service patterns and outcomes in complex cases when only a limited view can be gained using existing data. The discussion also explores how methodologies can adapt to an evaluation in these circumstances.

This paper examines the use of data routinely collected by local authorities (LAs) as part of the evaluation of innovation. Issues entailed are discussed and illustrated through two case studies of evaluations conducted by the research team within the context of children’s social care in England.

The quantitative analysis of LA data can play an important role in evaluating innovation but researchers will need to address challenges related to: selection of a suitable methodology; identifying appropriate comparator data; accessing data and assessing its quality; and sustaining and increasing the value of analytic work beyond the end of the research. Examples are provided of how the two case studies experienced and addressed these challenges.

• Quasi-experimental methods can be beneficial tools for understanding the impact of innovation in children’s services, but researchers should also consider the complexity of children’s social care and the use of mixed and appropriate methods. • Those funding innovative practice should consider the additional burden on those working with data and the related data infrastructure if wishing to document and analyse innovation in a robust way. • Data, which may be assumed to be uniform may in fact not be when considered at a multi-area or national level, and further study of the data recording practice of social care professionals is required.

The paper discusses some common issues experienced in quasi-experimental approaches to the quantitative evaluation of children’s services, which have, until recently, been rarely used in the sector. There are important considerations, which are of relevance to researchers, service leads in children’s social care, data and performance leads and funders of innovation.