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Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator.

The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module.

The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature.

A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors.

Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image.

Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder.

Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time.

Recently, the modelling and simulation of switched systems containing new nonlinear components in electronics and power electronics industry have gained importance. In this paper, both feed‐forward artificial neural networks (ANN) and adaptive network‐based fuzzy inference systems (ANFIS) have been applied to switched circuits and systems. Then their performances have been compared in this contribution by developed simulation programs. It has been shown that ANFIS require less training time and offer better performance than those of ANN. In addition, ANFIS using “clustering algorithm” to generate the rules and the numbers of membership functions gives a smaller number of parameters, better performance and less training time than those of ANFIS using “grid partition” to generate the rules. The work not only demonstrates the advantage of the ANFIS architecture using clustering algorithm but also highlights the advantages of the architecture for hardware realizations.

An electronic assembly may consist of a printed circuit and various types of electrical components. Soldering to make the electrical/mechanical connection is a critical process. Both printed circuit and component leads must promote acceptable solder wetting if high reliability is to be obtained. Bulk purchasing of these items can lead to long periods of storage often in poor conditions. This paper describes some of the work which simulates storage conditions by accelerated ageing so that a prediction can be made as to whether solderability will be affected. Due acknowledgement is hereby made to the EIPC for their permission to publish this paper which was presented at a recent EIPC seminar.

Advantages of using high speed and thermal analysis tools in a tightly integrated design environment are presented. The time to market, the quality of advanced technology designs, and the often assumed reliability of a product are all becoming the responsibility of the layout engineer. To ensure the success of the end‐product the designer must have available tightly integrated product design tools. They must reliably predict potential problems, such as transmission line delays, signal noise, device over‐heating etc., and therefore reduce multiple design iterations by producing designs that are correct first time.

This paper reports further development and applications of a computational model permitting analysis of frequency response characteristics of simulated neurons. The original single‐neuron model, as described by Peddicord and Sampson in 1974, is briefly reviewed here. There follows a thorough description of a new interactive implementation of the model on a PDP‐11/45. The implementation permits high‐speed simulation of large neural networks, and is designed for easy use by investigators with no special knowledge of computers or programming. Experiments with the new system have included the design of improved bandpass filters, pacemaker neurons and networks, and a cerebellar circuit. Simulation results are presented and, in the last case, compared with available physiological data. The paper concludes with a critique of the system, suggestions for further experiments, and a comparison with the simulation system developed by Perkel. Two appendices document the system data structures and show a sample simulation run.

The paper presents an efficient methodology that was developed for the reliability prediction and the failure mode effects and criticality analysis (FMECA) of electronic devices using fuzzy logic.

The reliability prediction is based on the general features and characteristics of the MIL‐HDBK‐217FN2 technical document and a derating plan for the system design is developed in order to maintain low components’ failure rates. These failure rates are used in the FMECA, which uses fuzzy sets to represent the respective parameters. A fuzzy failure mode risk index is introduced that gives priority to the criticality of the components for the system operation, while a knowledge base is developed to identify the rules governing the fuzzy inputs and output. The fuzzy inference module is Mamdani type and uses the min‐max implication‐aggregation.

A typical power electronic device such as a switched mode power supply was analyzed and the appropriate reliability indices were estimated using the stress factors of the derating plan. The fuzzy failure mode risk indices were calculated and compared with the respective indices calculated by the conventional FMECA.

Further research efforts are needed for the application of fuzzy modeling techniques in the area of reliability assessment of electronic devices. These research efforts can be concentrated in certain applications that have practical value.

Practical applications can use a fuzzy FMECA modeling instead of the classical FMECA one, in order to obtain a more accurate analysis.

Fuzzy modeling of FMECA is described which can calculate fuzzy failure mode risk indices.

The malfunction variables of power stations are related to the areas of weather, physical structure, control and load behaviour. To predict temporal power failure is difficult due to their unpredictable characteristics. As high accuracy is normally required, the estimation of failures of short-term temporal prediction is highly difficult. This study presents a method for converting stochastic behaviour into a stable pattern, which can subsequently be used in a short-term estimator. For this conversion, K-means clustering is employed, followed by Long-Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU) algorithms are used to perform the Short-term estimation. The environment, the operation and the generated signal factors are all simulated using mathematical models. Weather parameters and load samples have been collected as part of a data set. Monte-Carlo simulation using MATLAB programming has been used to conduct experimental estimation of failures. The estimated failures of the experiment are then compared with the actual system temporal failures and found to be in good match. Therefore, for any future power grid, there is a testbed ready to estimate the future failures.

The Van Roosbroeck semiconductor device equations are put into useful analogy with the Arrhenius equations of combustion theory. Both, when written in appropriate variables, enjoy (suffer) exponential nonlinearities. Here, we present this analogy in rather simple terms. It is proposed that this analogy be further developed.

An evaluation programme involving the extensive thermal cycling of component‐assembled printed circuit boards has been undertaken to assess the suitability of ESA‐approved hand‐soldering techniques for use on long‐life satellites. The modes of joint degradation are discussed and the metallurgical changes that result from material thermal expansion mismatch and repeated strain within the solder alloy (63% tin, 37% lead) are highlighted by photomicroscopy.