Search results

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels.

The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented.

The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%.

The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

This paper aims to review comprehensively the different voltage-boosting techniques and classifies according to their voltage gain, stress on the semiconductor devices, count of the total components and their prominent features. Hence, the focus is on non-isolated step-up converters. The converters categorized are analyzed according to their category with graphical representation.

Many converters have been reported in recent years in the literature to meet our power requirements from mill watts to megawatts. Fast growth in the generation of renewable energy in the past few years has promoted the selection of suitable converters that directly impact the behaviour of renewable energy systems. Step-up converters are a fast-emerging switching power converter in various power supply units. Researchers are more attracted to the derivation of novel topology with a high voltage gain, low voltage and current stress, high efficiency, low cost, etc.

A comparative study is done on critical metrics such as voltage gain, switch voltage stress and component count. Besides, the converters are also summarized based on their advantages and disadvantages. Furthermore, the areas that need to be explored in this field are identified and presented.

Types of analysis usually performed in dc converter and their needs with the areas need to be focused are not yet completely reviewed in most of the articles. This paper gives an eyesight on these topics. This paper will guide the researchers to derive and suggest a suitable topology for the chosen application. Moreover, it can be used as a handbook for studying the various topologies with their shortfalls, which will provide a way for researchers to focus.

The main purpose of this paper is to select appropriate voltage vectors in the switching techniques and, by selecting the proper voltage vectors, be able to achieve a DC link with the same outputs and a symmetric multi-level inverter.

The proposed structure, a two-stage DC–AC symmetric multi-level inverter with modified Model Predictive Control (MMPC) method, is presented for Photovoltaic (PV) applications. The voltage of DC-link capacitors of the boost converter is controlled by MMPC control method to select appropriate switching vectors for the multi-level inverter. The proposed structure is provided for single-phase power system, which increases 65 V input voltage to 220 V/50 Hz output voltage, with 400 V DC link. Simulation results of proposed structure with MMPC method are carried out by PSCAD/EMTDC software.

Based on the proposed structure and control method, total harmonic distortion (THD) reduces, which leads to lower power losses and higher circuit reliability. In addition, reducing the number of active switches in current path causes to lower voltage stress on the switches, lower PV leakage current and higher overall efficiency.

In the proposed structure, a new control method is presented that can make a symmetric five-level voltage with lower THD by selecting proper switching for PV applications.

At first, the organic/inorganic and hybrid PV materials by their electrical model are described. Then the proposed converter topology, circuit analysis and various operating modes of converter according to on/off timing of switches are investigated. The current and voltage in the converter components are illustrated and the voltage gain and switching stress of proposed converter are presented. Finally, to show the effectiveness of the proposed converter, the power loss analysis is provided and the simulation is done in PSIM software. In the last section, the advantages of the proposed topology of higher efficiency by lower number of components in compare with other conventional topologies are presented.

In this paper, an improved topology of DC-DC converter based on VL technique is proposed for Perovskite Solar cells (PeSCs). The PeSCs attracted a lot of interest due to their potential in combining the advantages of both organic and inorganic components. The proposed converter by using fewer components and higher output voltage generation in compare with conventional ones could be a good candidate for PeSCs due to lower efficiency of this cells. The performance of converter is expressed in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), and the boundary conditions for the proposed converter is presented.

By using VL technique, this converter is used to boost the lower output voltage levels of PeSCs for grid connection. The PV cell output voltage is increased from 24.5 V to 106 V by proposed converter topology. The step-by-step voltage increasing by charging and discharging of inductor and capacitor is used for boosting the input voltage. By comparing other converters, there is no design complexity in the proposed converter structure, and the power loss is much reduced which increases the converter efficiency. On the other hand, due to using lower number of elements of energy storage elements such as inductors and capacitors, the converter cost is also diminished. Therefore, the design topology simplicity which result simple control algorithm and lower number of components which diminish the system cost by appropriate voltage boosting capability are the main advantages of this proposed topology for new PeSCs which don’t have enough efficiency in compare with old Si PV cells.

In this paper, by using the lower number of components a new structure of DC-DC converter based on the VL technique is proposed. The advantages of this converter such as the simplicity, easier control and high voltage gain by lower power loss, could make this converter a good candidate for new PeSCs where the system whole efficiency will be a critical point to have the unique properties of this new materials in lower loss.

Real‐time multiplication of two analog signals is one of the most important operations in analogue signal processing. Driven by low‐power and low‐voltage requirements for integrated mixedsignal portable applications, the paper's aim is to propose a novel four‐quadrant low‐voltage analog multiplier using dynamic threshold MOS transistors (DTMOS).

The SPICE simulations were performed with 0.25 μm technology parameters and results verify the performance of the circuit. The multiplier is simulated at low‐supply voltage of ±0.5 V.

The proposed multiplier has high linearity and simple structure hence it is suitable for high‐performance and low‐power analog VLSI applications.

A new low‐voltage four quadrant analog multiplier using DTMOS circuit topology is presented in the paper.

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.

This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.

The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.

Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.

GNRFET devices are suitable for implementing low power and high density SRAM cell.

The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.

This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

The purpose of this paper is to investigate how the dc-link voltage for the converter of a wind generator should be selected, i.e. to determine the losses in the generator and the converter when using various dc-link voltage levels.

To presents the efficiency evaluation of 5 MW wind turbine generating systems, two 5 MW surface mounted permanent magnet synchronous generators (PMSG) with medium and low rated voltage is designed. A two-level transistor converter is considered for ac/dc conversion. Three different dc-link voltage levels are used. By using these voltage levels the PMSG is utilized in slightly different ways.

It is found that the system with the lower voltage machine has slightly higher annual energy efficiency compare to the higher voltage system. Furthermore, it is shown that the best choice for the dc-link voltage level is a voltage between the minimum voltage which gives the desired torque and the voltage which gives Maximum Torque Per Ampere.

A procedure as well as investigations with quantified results on how to find the highest complete drive system efficiency for a wind turbine application. Based on two given PMSG, the most energy-efficient dc-link voltage has been established.

The purpose of this paper is to design the control for a new type of DC converter that can be used in low voltage and low power DC drives, e.g. in cars and robots.

Based on the theory of the switching systems, the existence condition of the limit cycle for the novel DC/DC converter is formulated.

The feed forward control which realizes the limit cycle is designed. The first experimental results show that the designed control of the DC/DC converter is effective in solving the control problem of DC drives and allows the use of a low input voltage as power source for the standard DC drive.

Today DC/DC converters play a key role in power conversion and distribution. The presented DC/DC converter has a very simple circuit and allows changing the output voltage in the wide range that is needed for the DC drive control.

This study aims to investigate the effect of electrodeposition parameters (i.e. time and voltage) on the properties of hydroxyapatite (HA) coating fabricated on Ti6Al4V surface.

A full factorial design along with response surface methodology was utilized to evaluate the main effect of independent variables and their relative interactions on response variables. The effect of electrodeposition voltage and deposition time on HA coatings Ca/P molar ratio and the size of deposited HA crystals were examined by structural equation modeling (SEM). The formation of plate-like and needle-like HA crystals was observed for all experiments.

The results obtained showed that the higher electrodeposition voltage leads to lower Ca/P values for HA coatings. This is more significant at lower deposition times, where at a 20-minute deposition time, the voltage increased from 2 to 3 V and the Ca/P decreased from 2.27 to 1.52. Full factorial design results showed that electrodeposition voltage has a more significant effect on the size of the deposited HA crystal. With increasing the voltage from 2 to 3 V at a deposition time of 20 min, the HA crystal size varied from 99 to 36 µm.

The investigation delved into the impact of two critical parameters, deposition time and voltage, within the electrodeposition process on two paramount properties of HA coatings. Analyzing the alterations in coating characteristics relative to variations in these process parameters can serve as a foundational guide for subsequent research in the domain of calcium-phosphate deposition for implants.