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Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels.

The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented.

The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%.

The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.

Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.

This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.

All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs).

To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism.

The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET.

This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.

The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.

The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. I_on/I_ambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.

The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

The purpose of this paper is to analyze and optimize the formation of field-effect heterotransistors using analytical approach. The approach makes it possible to analyze mass and heat transport in a multilayer structure without cross-linking of solutions on interfaces between layers of the multilayer structure. The optimization makes it possible to decrease dimensions of the heterotransistors and to increase speed of transport of charge carriers during functioning of the transistors.

The authors introduce an analytical approach for analysis of mass and heat transport, which makes it possible to take into account at one time varying in space and time parameters of the transports (diffusion coefficient, heat conduction coefficient, etc.) and nonlinearity of processes. The approach enables analysis of mass and heat transport in a multilayer structure without cross-linking of solutions on interfaces between layers of the multilayer structure and optimises the technological process. The optimization means it is possible to decrease dimensions of field-effect heterotransistors.

In this paper the authors introduce an approach to manufacture a field-effect heterotransistor with inhomogeneous doping of channel. Some recommendations to optimize technological process to manufacture more compact distribution of concentration of dopant have been formulated.

The results are original and the paper provides an approach to the manufacture of a field-effect heterotransistor.

This study aims to investigate the effects of indium composition on surface morphology and optical properties of indium gallium nitride on gallium nitride (InGaN/GaN) heterostructures.

The InGaN/GaN heterostructures were grown on flat sapphire substrates using a metal-organic chemical vapour deposition reactor with a trimethylindium flow rate of 368  sccm. The indium composition of the InGaN epilayers was controlled by applying different substrate temperatures. The surface morphology and topography were observed using field emission scanning electron microscope (F.E.I. Nova NanoSEM 450) and atomic force microscopy (Bruker Dimension Edge) with a scanning area of 10 µm × 10 µm, respectively. The compositional analysis was done by Energy Dispersive X-Ray Analysis. Finally, the ultraviolet-visible (UV-Vis) spectrophotometer (Agilent Technology Cary Series UV-Vis-near-infrared spectrometer) was measured from 200 nm to 1500 nm to investigate the optical properties of the samples.

The InGaN/GaN thin films have been successfully grown at three different substrate temperatures. The indium composition reduced as the temperature increased. At 760 C, the highest indium composition was obtained, 21.17%. This result was acquired from the simulation fitting of ω−2θ scan on (0002) plane using LEPTOS software by Bruker D8 Discover. The InGaN/GaN shows significantly different surface morphologies and topographies as the indium composition increases. The thickness of InGaN epilayers of the structure was ∼300 nm estimated from the field emission scanning electron microscopy. The energy bandgap of the InGaN was 2.54 eV – 2.79 eV measured by UV-Vis measurements.

It can be seen from this work that changes in substrate temperature can affect the indium composition. From all the results obtained, this work can be helpful towards efficiency improvement in solar cell applications.

The purpose of this paper was to present the results of the three types of FG transistors that were investigated. The reliability issues of oxide thickness due to programming, fabrication defects and process variation may cause leakage currents and thus charge retention failure in the floating gate (FG).

The tunnelling and electron injection methods were applied to program FG devices of different lengths (180 and 350 nm) and coupling capacitor sizes. The drain current and threshold voltage changes were determined for both gate and drain voltage sweep. The devices were fabricated using IBM 130 nm process technology.

Current leakages are increasing with device scaling and reducing the charge retention time. During programming, charge traps may occur in the oxide and prevent further programming. Thus, the dominant factors are the reliability of oxide thickness to avoid charge traps and prevent current/charge leakages in the FG devices. The capacitive coupling (between the tunnelling and electron injection capacitors) may contribute to other reliability issues if not properly considered.

Although the results have raised further research questions, as revealed by certain reliability issues, they have shown that the use of FGs with nanoscale technology is promising and may be suitable for memory and switching applications.

Challenges to a robust and accurate implementation of electric‐field‐enhanccd thermal‐generation mechanisms in a drift‐diffusion‐based semiconductor‐device simulation code are discussed and solutions proposed. The implementation of the physical models and associated numerical methods is applied to the simulation of leakage currents in trench‐DRAM cells.