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The high-frequency common-mode voltage introduced by power converters, using conventional modulation techniques, results in common-mode current that has the potential to cause physical damage to the shaft and bearings of electric drives as well as unwanted tripping of ground fault relays in motor drives and electrical networks. The paper aims to provide a complete elimination of common mode voltage using a matrix converter (MC) with a new modulation strategy that reduces the size of the power converter system considerably. Further, a new MC topology is proposed to eliminate the common mode voltage with improved voltage transfer ratio (VTR).

The direct MC topology is selected, as it is the only converter topology that has the potential to eliminate common mode voltage in direct AC to AC systems. Using the rotating space vector technique, common mode voltage is eliminated but this reduces the VTR of the converter. To improve the VTR, a modified MC topology with a modified rotating space vector strategy is proposed. In addition, for improving the power factor at the input, the input current control strategy is developed.

The use of rotating space vector technique eliminates the common mode voltage even under all input abnormalities like unbalance and harmonics. By applying positive and negative rotating space vectors, input power factor control can be achieved. However, the control range is limited from unity power factor to the output power factor. It is observed that in the current controlled technique the modulation index reduces further. It is also found that there is a reduction in switching stresses of individual switches in proposed topology compared to direct MC topology.

In this paper, a modified rotating space vector technique is applied to the proposed converter topology for elimination of common mode voltage with an increased VTR. The topology can be used for common mode voltage elimination in existing electric drives without the need for modifying the drive system.

The purpose of this paper is to evaluate the conditions in which a saturation of the common mode (CM) choke might appear to be essential for proper design of the CM voltage filters. This paper presents a method for the determination of a CM choke flux density produced by multilevel inverters with carrier‐based modulations.

The proposed combination of secant and tangent methods allows efficient and high‐resolution determination of the CM voltage waveforms produced at the output of the multilevel inverters with commonly used carrier‐based modulations.

The presented results show that the application of a five‐level inverter with specific modulation causes a decrease of the maximum flux density, down to 15 per cent of the maximum level of the flux density reached in a two‐level inverter. The proposed, dedicated approximation method provides an accuracy of the root estimation better by about three orders for a comparable number of the function calls in comparison with Brent's method.

The presented theoretical evaluations make possible the determination of the maximum expected value of the flux density produced by multilevel inverters with various types of carrier‐based modulations, which allows a reduction in dimensions, weight and cost of CM chokes applied in CM voltage compensators.

In the paper, the new formulas that describe the placement of triangular carrier functions for commonly used multilevel inverters have been presented. In order to avoid accumulation of the estimation error, during determination of the CM voltage time integral, a dedicated, efficient method of roots approximation has been developed.

Maintaining a balanced neutral point, reducing power loss, execution time are important criteria for the controlling of neutral point clamped (NPC) inverter. However, it is tough to meet all the challenges and also supplying the load current within the harmonic limit. This paper aims to maintain load current quality within the Institute of Electrical and Electronics Engineers 519 standard and meet the above-mentioned challenges.

The output load current of a three-level simplified neutral point clamped (3 L-SNPC) inverter is controlled in this paper using model predictive control (MPC). The 3 L-SNPC inverters is considered because fewer semiconductor devices are used in this topology; this will enhance the reliability of the system. MPC is used as a controller because it can handle the direct current-link capacitors’ voltage balancing problem in a very intuitive way. The proposed 3 L-SNPC yields similar current total harmonic distortion (THD), transient and steady-state responses, voltage stress and over current protection capability as the conventional NPC inverter. To reduce the computational burden of the proposed SNPC system, two simplified MPC strategies are proposed, namely, single voltage vector prediction-based MPC and selective voltage vector prediction-based MPC.

The system shows a current THD of 2.33% at 8.96 kHz. The overall loss of the system is reduced significantly to be useful in medium power applications. The required execution times for the simplified MPC strategies are tested on the hardware dSPACE 1104 platform. It is found that the single voltage vector prediction-based MPC and the selective voltage vector prediction-based MPC are computationally efficient by 8.28% and 62.9%, respectively, in comparison with the conventional MPC-based conventional NPC system.

Multiple system constraints are considered throughout the paper and also compare the SNPC to the conventional NPC inverter. Proper current tracking, over-current protection, overall power loss reduction especially switching loss and maintaining capacitor voltages balance at a neutral point are achieved. The improvement of execution time has also been verified and calculated using hardware-in-loop of the dSPACE DS1104 platform.

This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.

A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P_−1dB), power dissipation and reduction of switching quad C_gs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.

A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P_−1dB in 0.18‐μm CMOS technology.

The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.

The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.

In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

The lightning phenomenon is one of the main threats in photovoltaic (PV) applications. Suitable protection systems avoid major damages from direct strikes but also nearby strikes may induce overvoltage transients in the module itself and in the power conditioning circuitry, which can permanently damage the system. The effects on the PV system sensibly depend on the converter topology and on the adopted power switch. In the present study, a comparative analysis of the transient response due to a nearby lightning strike (LS) is carried out for three PV systems, each equipped with a different converter, namely, boost, buck and buck–boost, based on either silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFET) or insulated gate bipolar transistors controlled power switch devices, allowing in this way an analysis at different switching frequencies. The purpose of this paper is to present the results of the numerical analysis to help the design of suited protection systems.

Using a recently introduced three-dimensional semi-analytical method to simulate the electromagnetic transients caused in PV modules by nearby LSs, we investigate numerically the effect of a LS on the electronic circuits connecting the module to the alternate current (AC) power systems. This study adopts numerical simulations because experimental analyses are not easy to perform and does not grant a sufficient coverage of all statistically relevant aspects. The approach was validated in a previous paper against available experimental data.

It is found that the load voltage is not severely interested by the strike effects, thanks to the low pass filters present at the converter output, whereas a relatively high overvoltage develops between the negative pin of the inner circuitry and the “ground” voltage reference. The overcurrent present in the active switches is hardly comparable because of the different topologies and working frequencies; however, the highest overcurrent is observed in the buck converter topology, with SiC MOSFET technology, although it shows the fastest decay.

This research proposes, to the best of the authors’ knowledge, a comprehensive comparison of the indirect lighting strike effects on the converter connected to PV panels. A proper design of the lightning and surge protection system should take into account such aspects to reduce the risk of induced overvoltage and overcurrent transients.

An explanation of techniques for the connection of sensors to data acquisition systems and how to stop noise swamping your signal.

Wind energy has matured to a level of development at which it is ready to become a generally accepted power generation technology. The aim of this paper is to provide a brief review of the state of the art in the area of electrical machines and power‐electronic systems for high‐power wind energy generation applications. As the first part of this paper, latest market penetration, current technology and advanced electrical machines are addressed.

After a short description of the latest market penetration of wind turbines with various topologies globally by the end of 2010 is provided, current wind power technology, including a variety of fixed‐ and variable‐speed (in particular with doubly‐fed induction generator (DFIG) and permanent magnet synchronous generator (PMSG) supplied with partial‐ and full‐power converters, respectively) wind power generation systems, and modern grid codes, is presented. Finally, four advanced electrical‐machine systems, viz., brushless DFIG, open winding PMSG, dual/multi 3‐phase stator‐winding PMSG and magnetic‐gear outer‐rotor PMSG, are identified with their respective merits and challenges for future high‐power wind energy applications.

For the time being, the gear‐drive DFIG‐based wind turbine is significantly dominating the markets despite its defect caused by mechanical gears, slip rings and brush sets. Meanwhile, direct‐drive synchronous generator, especially utilizing permanent magnets on its rotor, supplied with a full‐capacity power converter has become a more effective solution, particularly in high‐power offshore wind farm applications.

This first part of the paper reviews the latest market penetration of wind turbines with a variety of mature topologies, by summarizing their advantages and disadvantages. Four advanced electrical‐machine systems are selected and identified by distinguishing their respective merits and challenges for future high‐power wind energy applications.

This paper aims to propose a new transformer-less inverter structure to reduce the common-mode leakage current in grid-connected photovoltaic (PV) systems.

The proposed circuit structure is the same as the conventional full-bridge inverter with three additional power switches in a triangular structure. These three power switches are between the bridge and the output filter, and they mitigate the common-mode leakage current flowing toward the PV panels’ capacitors. The common-mode leakage current mitigation is done through the three-direction clamping cell (TDCC) concept. By clamping the common-mode voltage to the middle voltage of the DC-link capacitors, the leakage current and the total harmonic distortion (THD) of the injected current to the grid is effectively reduced. Therefore, the efficiency is improved.

The switching modes and the control method are introduced. A comparison is carried out between the proposed structure and other solutions in the literature. The proposed topology and its respective control method are simulated by PSCAD/EMTDC software. The simulation results validate the advantages of the presented structure such as clamping the common-mode voltage and reducing leakage current and THD of injected current to the grid.

Presenting a single phase-improved inverter structure with low-leakage current for grid-connected PV power systems represents a significant original contribution to this work. The proposed structure can inject a sinusoidal current with low THD to the AC grid, and the power factor is unity on the AC side. In the half positive cycle, one of the switches in the TDCC is turned off under zero current. Besides, one of the other switches in TDCC is turned on with zero voltage and, therefore, its turn-on switching losses are zero. The efficiency of the proposed topology is high because of the reduction of leakage current and power losses. Accordingly, the presented topology can be a good solution to the leakage current elimination.

The purpose of this paper is to present an analysis of common mode oscillations of several kilohertz in electrical drive systems. The analysed oscillations occur especially in electrical drive systems with active front end (AFE), common DC link and long motor cables and are independent of the well‐known reflection phenomenon. Owing to the resulting overvoltages, the motor isolation lifetime may be significantly reduced.

For the analysis of the described problem, all parts of the common mode system of an electrical drive system are carefully modelled. This leads to an analysis of the frequency behaviour of the common mode system. The excitation mechanisms are also analysed and simulation in the time domain is performed to show the resulting overvoltages. Finally, measurements confirm the findings.

The investigations identified the reasons for the oscillations: the common mode system behaviour, including the common mode resonant behaviour of some special kinds of motor. Furthermore, the excitation mechanism is found to be dependent on the modulation schemes of the AFE and the inverters. Accordingly, a special remedy concerning the modulation is derived and compared to other known remedies. The results of the simulations show the good efficiency of the proposed remedy.

The presented results describe important basics for the development of electrical drive systems. By taking these issues into consideration, many unpredictable failures can be avoided.

In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.

Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.

This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.

Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.