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Lack of optimization and improvement on experimental circuits precludes comprehensive statements. It is a deficiency of the existing chaotic circuit technology. One of the aims of this paper is to solve the above mentioned problems. Another purpose of this paper is to construct a 10 + 4-type chaotic secure communication circuit based on the proposed third-order 4 + 2-type circuit which can output chaotic phase portraits with high accuracy and high stability.

In Section 2 of this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new third-order Lorenz-like chaotic system is proposed based on the 4 + 2 circuit. Then some simulations are presented to verify that the proposed system is chaotic by using Multisim software. In Section 3, a fourth-order chaotic circuit is proposed on the basis of the third-order 4 + 2 chaotic circuit. In Section 4, the circuit design method of this paper is applied to chaotic synchronization and secure communication. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. In Section 5, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented in an analog electronic circuit. The analog circuit implementation results match the Multisim results.

The simulation results show that the proposed fourth-order chaotic circuit can output six phase portraits, and it can output a stable fourth-order double-vortex chaotic signal. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. The scheme has the advantages of clear thinking, efficient and high practicability. The experimental results show that the precision is improved by 2-3 orders of magnitude. Signal-to-noise ratio meets the requirements of engineering design. It provides certain theoretical and technical bases for the realization of a large-scale integrated circuit with a memristor. The proposed circuit design method can also be used in other chaotic systems.

In this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new chaotic system is proposed on the basis of the 4 + 2 chaotic circuit for the first time. Some simulations are presented to verify its chaotic characteristics by Multisim. Then the novel third-order 4 + 2 chaotic circuit is applied to construct a fourth-order chaotic circuit. Simulation results verify the existence of the new fourth-order chaotic system. Moreover, a new 10 + 4-type chaotic secure communication circuit is proposed based on chaotic synchronization of the novel third-order 4 + 2 circuit. To illustrate the effectiveness of the proposed scheme, the intensity limit and stability of the transmitted signal, the characteristic of broadband and the requirements for accuracy of electronic components are presented by Multisim simulation. Finally, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented through an analog electronic circuit, which are characterized by their high accuracy and good robustness. The analog circuit implementation results match the Multisim results.

Analog designers working infields such as aerospace, the defense and nuclear industries, telecommunications and medical electronics have long faced a special problem when trying to source application‐specific integrated circuits (ASICs) for their designs. Although digital ASICs have long been available with the degree of radiation hardening normally required for these applications, sourcing radiation‐hardened (‘rad‐hard’) analog ASICs has been much more difficult. In particular, the CMOS/SOS technology used very successfully to produce rad‐hard digital ASICs has long been considered to be fundamentally unsuitable for analog designs. Only now has CMOS/SOS technology been developed to the point where highly integrated, high‐performance rad‐hard analog ASICSs can be made readily available — thanks to a breakthrough by Swedish semiconductor specialists ABB HAFO that is now opening up new opportunities for analog designers everywhere.

In this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals.

A Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results.

It is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators.

Two new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

In this paper, we study the effect on the performance of a single supply low voltage operational amplifier due to such a mismatch.

We start with a given set of specifications and design a MOSFET based operational amplifier meeting those specifications. We then compute various parameters of the operational amplifier using PSPICE to verify that the amplifier meets the specifications. We create mismatch in three characteristics of differential pair MOSFETs: zero biased threshold voltage (V_th0), channel length (L) and process transconductance parameter (K). The effect of the mismatch on two performance parameters: (a) differential mode gain and (b) output DC voltage is then studied.

The effects of mismatch in MOSFET characteristics on the performance of single supply low voltage operational amplifiers are studied. Circuit designers can use the results to design operational amplifiers and other analog circuits to minimize the effects of such a mismatch on the performance of their circuits. In some cases, such a mismatch may even be desirable to obtain a desired performance from the circuit.

Circuit designers can use the results to design operational amplifiers and other analog circuits to minimize the effects of such a mismatch on the performance of their circuits.

Effect of mismatch of the transistor characteristics on the performance of circuits rarely reported in literature. This study is presented to aid circuit designers in designing circuits with enhanced performance.

Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator.

The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module.

The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature.

A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

The development of a sensor microsystems containing all the components of data acquisition system, such as sensors, signal‐conditioning circuits, analog‐digital converter, interface circuits and embedded microcontroller (MCU), has become the focus of attention in many biomedical applications. A review of the microsystems technology is presented in this paper, along with a discussion of the recent trends and challenges associated with its developments. A basic description of each sub‐system is also given. This includes the different front end, mixed analog‐digital, power management, and radio transmitter‐receiver circuits. These sub‐system designs are presented and discussed in a comparative study and final remarks are made. The performance of each sub‐system is assessed regarding many aspects related to the overall system performance.

The purpose of this paper is to develop a simple chaotic circuit. The circuit can be fabricated by less discrete electronic components, within which complex dynamical behaviors can be generated.

A second-order non-autonomous inductor-free chaotic circuit is presented, which is obtained by introducing a sinusoidal voltage stimulus into the classical Wien-bridge oscillator. The proposed circuit only has two dynamic elements, and its nonlinearity is realized by the saturation characteristic of the operational amplifier in the classical Wien-bridge oscillator. After that, its dynamical behaviors are revealed by means of bifurcation diagram, Lyapunov exponent and phase portrait and further confirmed using the 0-1 test method. Moreover, an analog circuit using less discrete electronic components is implemented, and its experimental results are measured to verify the numerical simulations.

The equilibrium point located in a line segment varies with time evolution, which leads to the occurrence of periodic, quasi-periodic and chaotic behaviors in the proposed circuit.

Unlike the previously published works, the significant values of the proposed circuit with simple topology are inductor-free realization and without extra nonlinearity, which make the circuit can be used as a paradigm for academic teaching and experimental illustraction for chaos.

To develop a wireless sensor micro‐systems containing all the components of data acquisition system, such as sensors, signal‐conditioning circuits, analog‐digital converter, embedded microcontroller unit (MCU), and RF communication modules. This has now become the focus of attention in many biomedical applications.

The system prototype consists of miniature FSK transceiver integrated with MCU in one small package, chip antenna, and capacitive interface circuitry based on Delta‐sigma modulator. At the base station side, an FSK receiver/transmitter is connected to another MCU unit, which send the received data or received instructions from a PC through a graphical user interface GUI. Industrial, scientific and medical band RF (433 MHz) was used to achieve half duplex communication between the two sides. A digital filtering has been used in the capacitive interface to reduce noise effects forming capacitance to digital converter. All the modules of the mixed signal system are integrated in a printed circuit board of size 22.46 × 20.168 mm.

An innovation circuits and system techniques for building advanced smart medical devices have been discussed. Low‐power consumption and high reliability are among the main criteria that must be given priority when designing such wirelessly powered microsystems. Switched capacitors readout circuits have been found to be suitable for pressure sensing low‐power applications.

The presented wireless prototype needs a second phase of development that will lead to a further reduction in both size and power consumption. Currently, the main limitation of the RF system is the number of working hours according to the selected battery.

The developed system was found to be useful in terms of measuring pressure and temperature in a system of either slow or fast physical change. It would be a good idea to explore the system performance in human or animal trials.

This paper fulfils useful information for capacitive interface circuitries and presents a new short‐range wireless system that has different design features.

The purpose of this paper is to design an intelligent ECG classifier using programmable IC technologies to implement many functional blocks of signal acquisition and processing in one compact device. The main microprocessor also simulates the TSK neuro-fuzzy classifier in testing mode to recognize the ECG beats. The design brings various theoretical solutions into practical applications.

The ECG signals are acquired and pre-processed using the Field-Programmable Analog Array (FPAA) IC due to the ability of precise configuration of analog parameters. The R peak of the QRS complexes and a window of 300 ms of ECG signals around the R peak are detected. In this paper we have proposed a method to extract the signal features using the Hermite decomposition algorithm, which requires only a multiplication of two matrices. Based on the features vectors, the ECG beats are classified using a TSK neuro-fuzzy network, whose parameters are trained earlier on PC and downloaded into the device. The device performance was tested with the ECG signals from the MIT-BIH database to prove the correctness of the hardware implementations.

The FPAA and Programmable System on Chip (PSoC) technologies allow us to integrate many signal processing blocks in a compact device. In this paper the device has the same performance in ECG signal processing and classifying as achieved on PC simulators. This confirms the correctness of the implementation.

The device was fully tested with the signals from the MIT-BIH databases. For new patients, we have tested the device in collecting the ECG signals and QRS detections. We have not created a new database of ECG signals, in which the beats are examined by doctors and annotated the type of the rhythm (normal or abnormal, which type of arrhythmia, etc.) so we have not tested the classification mode of the device on real ECG signals.

The compact design of an intelligent ECG classifier offers a portable solution for patients with heart diseases, which can help them to detect the arrhythmia on time when the doctors are not nearby. This type of device not only may help to improve the patients’ safety but also contribute to the smart, inter-networked life style.

The device integrate a number of solutions including software, hardware and algorithms into a single, compact device. Thank to the advance of programmable ICs such as FPAA and PSoC, the designed device can acquire one channel of ECG signals, extract the features and classify the arrhythmia type (if detected) using the neuro-fuzzy TSK network in online mode.