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Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.

This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.

The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.

Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.

GNRFET devices are suitable for implementing low power and high density SRAM cell.

The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.

This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Effective cooling is one of the challenges for photovoltaic thermal (PVT) systems to maintain the PV operating temperature. One of the best ways to enhance rate of heat transfer of the PVT system is using advanced working fluids such as nanofluids. The purpose of this research is to develop a numerical model for designing different form of thermal collector systems with different materials. It is concluded that PVT system operated by nanofluid is more effective than water-based PVT system.

In this research, a three-dimensional numerical model of PVT with new baffle-based thermal collector system has been developed and solved using finite element method-based COMSOL Multyphysics software. Water-based different nanofluids (Ag, Cu, Al, etc.), various solid volume fractions up to 3 per cent and variation of inlet temperature (20-40°C) have been applied to obtain high thermal efficiency of this system.

The numerical results show that increasing solid volume fraction increases the thermal performance of PVT system operated by nanofluids, and optimum solid concentration is 2 per cent. The thermal efficiency is enhanced approximately by 7.49, 7.08 and 4.97 per cent for PVT system operated by water/Ag, water/Cu and water/Al nanofluids, respectively, compared to water. The extracted thermal energy from the PVT system decreases by 53.13, 52.69, 42.37 and 38.99 W for water, water/Al, water/Cu and water/Ag nanofluids, respectively, due to each 1°C increase in inlet temperature. The heat transfer rate from heat exchanger to cooling fluid enhances by about 18.43, 27.45 and 31.37 per cent for the PVT system operated by water/Al, water/Cu, water/Ag, respectively, compared to water.

This study is original and is not being considered for publication elsewhere. This is also not currently under review with any other journal.

This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.

A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P_−1dB), power dissipation and reduction of switching quad C_gs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.

A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P_−1dB in 0.18‐μm CMOS technology.

The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.

The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.

In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

This study aim to use the finite volume method to solve differential equations related to three-dimensional simulation of a solar collector. Modeling is done using ANSYS-fluent software program. The investigation is done for a photovoltaic (PV) solar cell, with the dimension of 394 × 84 mm², which is the aluminum type and receives the constant heat flux of 800 W.m⁻². Water is also used as the working fluid, and the Reynolds number is 500.

In the present study, the effect of fluid flow path on the thermal, electrical and fluid flow characteristics of a PV thermal (PVT) collector is investigated. Three alternatives for flow paths, namely, direct, curved and spiral for coolant flow, are considered, and a numerical model to simulate the system performance is developed.

The results show that the highest efficiency is achieved by the solar cell with a curved fluid flow path. Additionally, it is found that the curved path’s efficiency is 0.8% and 0.5% higher than that of direct and spiral paths, respectively. Moreover, the highest pressure drop occurs in the curved microchannel route, with around 260 kPa, which is 2% and 5% more than the pressure drop of spiral and direct.

To the best of the authors’ knowledge, there has been no study that investigates numerically heat transfer, fluid flow and electrical performance of a PV solar thermal cell, simultaneously. Moreover, the effect of the microchannel routes which are considered for water flow has not been considered by researchers so far. Taking all the mentioned points into account, in this study, numerical analysis on the effect of different microchannel paths on the performance of a PVT solar collector is carried. The investigation is conducted for the Reynolds number of 500.

The purpose of this paper is to experimentally and numerically investigate the cooling performance of the air-to-water thermoelectric cooling system under different working conditions.

An air-to-water thermoelectric cooling system was designed and manufactured according to the principle of discrete binary thermoelectric Peltier modules, and the thermal performance, heat transfer rate and average COP values were examined at different cooling water temperatures and voltages applied. Additionally, numerical simulations were performed by computational fluid dynamics approach to investigate the temperature distribution and airflow structure inside the cooling chamber.

Analyses were performed using experimental tests and numerical methods. It was concluded that, by decreasing the cooling water temperature from 20 to 5 °C, the average COP increases about 36%. The voltage analysis showed that the efficiency of the system does not always increase as the voltage rises; more importantly, the optimum voltage is different and depends on whether it is desired to increase COP or increase the cooling rate.

In the studies published in the field of thermoelectric cooling systems, little attention has been paid to the voltage applied and its relationship to other operating conditions. In most cases, the tests are performed at a constant voltage. In this study, several options, including applied voltage and cooling water temperature, were considered simultaneously and their effects on performance have been tested. It was found that under such studies, optimization work should be done to evaluate maximum performance in different working conditions.

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

This paper aims to develop a selective energy optimisation of the photovoltaic–thermal (PV/T) system performance. The PV cell inside the PV/T system could be periodically manipulated to produce domestic hot water without applying an external power supply.

A numerical simulation model of the proposed PV/T model was developed in MATLAB/Simulink to analyse the selective energy optimisation of the model. The extrinsic cell resistance (R_se) is adjusted to control the ratio of thermal to the electrical energy, generated from the PV cell inside the PV/T system. Therefore, the internal heat of the PV cell inside the PV/T system is periodically used as a thermal element to produce electrical power and hot water.

The optimisation of PV/T energy shows that the electrical power efficiency can increase by 11.6% when R_se was 0 Ω, and the 200 L water tank temperature increased by 22ºC when R_se was 50 Ω.

This study showed that the use of the PV cell could be extended to domestic hot water and space heating, and not only for electricity.

This paper aims to present the fabrication and testing of a pressure sensor integrated with Hall effect sensors and permanent magnets arranged in two configurations to measure pressure in the range of 0–1 bar. The sensor is fabricated using stainless steel (SS) and can be used in high-temperature and highly corrosive environments. The fabricated sensor is of low cost, self-packaged and the differential arrangement helps in compensating for any ambient temperature variations.

The sensor deflects of a circular diaphragm with a simple rigid mechanical structure to convert the applied pressure to a Hall voltage output. Two sensor designs are proposed with a single pair of Hall sensors and magnets and a differential configuration with two Hall sensors and magnets. Two sensor designs are designed, fabricated and tested for their input–output characteristics and the results are compared.

The fabricated sensors are calibrated for 25 cycles of ascending and descending pressure in steps of 0.1 bar. Various static characteristics like nonlinearity, hysteresis and % error are estimated for both the sensor designs and compared with the existing Hall effect based pressure sensors. The differential arrangement design was found to have better characteristics as compared to the other design from the experimental data.

This paper focuses on fabricating and testing a novel differential Hall effect based pressure sensor. The differential arrangement of the sensor aids in the compensation of ambient temperature variations and the use of SS enables the sensor in high-temperature and highly corrosive applications. The proposed sensor is low cost, simple and self-packaged, and found to have high repeatability and good linearity compared to other similar Hall effect based pressure sensors available in the literature.