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The purpose of this paper is to develop a familiarity analysis of resistive-capacitive (RC) network active circuit operating with unfamiliar low-pass (LP) type negative group delay (NGD) behavior. The design method of NGD circuit is validated by simulation with commercial tool and experimental measurement.

The present research work methodology is structured in three main parts. The familiarity theory of RC-network LP-NGD circuit is developed. The LP-NGD circuit parameters are expressed in function of the targeted time-advance. Then, the feasibility study is based on the theory, simulation and measurement result comparisons.

The RC-network based LP-NGD proof of concept is validated with −1 and −0.5 ms targeted time-advances after design, simulation, test and characterized. The LP-NGD circuit unity gain prototype presents NGD cut-off frequencies of about 269 and 569 Hz for the targeted time-advances, −1 and −0.5 ms, respectively. Bi-exponential and arbitrary waveform signals were tested to verify the targeted time-advance.

The performance of the unfamiliar LP-NGD topology developed in the present study is limited by the parasitic elements of constituting lumped components.

The NGD circuit enables to naturally reduce the undesired delay effect from the electronic and communication systems. The NGD circuit can be exploited to reduce the delay induced by electronic devices and system.

As social impacts of the NGD circuit application, the NGD function is one of prominent solutions to improve the technology performances of future electronic device in term of communication aspect and the transportation system.

The originality of the paper concerns the theoretical approach of the RC-network parameters in function of the targeted time-advance and the input signal bandwidth. In addition, the experimental results are also particularly original.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).

This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.

This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.

This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.

This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.

Carpal tunnel syndrome (CTS) is a hand disease caused by the pressing of the median nerve present in the palmar side of the wrist. It causes severe pain in the wrist, triggering disturbance during sleep. Different products like splints, braces and gloves are available in the market to alleviate this disease but there was still a need to improve the wearability, comfort and cost of the product. This study was about designing a comfortable and cost-effective wearable system for mild-to-moderate CTS. Transcutaneous electrical nerve stimulation (TENS) therapy has been used to reduce the pain in the wrist.

After simulation by using Proteus software (which allowed the researchers to draw and simulate electrical circuits using ISIS, ARES and PCB design tools virtually), the circuit with optimum frequency, i.e. 33 Hz was selected, and the circuit was developed on a printed circuit board (PCB). The developed circuit was integrated successfully into the half glove structure.

The developed product had good thermophysiological comfort and hand properties as compared to the commercially available product of the same kind. In vivo testing (It involves the testing with living subjects like animals, plants or human beings) was performed which resulted in 85% confirmed viability of the product against CTS. A glove with an integrated circuit was developed successfully to accommodate various sizes without any sex specifications in a cost-effective way to mitigate the issue of CTS.

Industrial workers, individuals frequently using their hands or those diagnosed with CTS may wish to use this product as therapy. The attention could not be paid to the aesthetic or visual appeal of the developed product.

A very comfortable glove with integrated TENS electrodes was developed successfully to accommodate various sizes without any sex specifications in a cost-effective way to mitigate the issues of CTS.

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.

This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.

Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.

According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.

Process mining has emerged in the last decade as one of the most promising tools to discover and understand the actual execution of processes. This paper addresses the application of process mining techniques to analyze the performance of automatic guided vehicles (AGVs) in one of the Body in White circuits of the factory that Stellantis has in Vigo, Spain.

Standard process mining discovery and conformance algorithms are applied to analyze the different AGV execution paths, their lead times, main sources and identify any unexpected potential situations, such as unexpected paths or loops.

Results show that this method provides very useful insights which are not evident for logistics technicians. Even with such automated devices, where the room for decreased efficiency can be apparently small, process mining shows there are cases where unexpected situations occur, leading to an increase in circuit times and different variants for the same route, which pave the road for an actual improvement in performance and efficiency.

This paper provides evidence of the usefulness of applying process mining in manufacturing processes. Practical applications of process mining have traditionally been focused on processes related to services and management, such as order to cash and purchase to pay in enterprise resource planning software. Despite its potential for use in industrial manufacturing, such contributions are scarce in the current state of the art and, as far as we are aware of, do not fully justify its application.

This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.

The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.

Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.

The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.