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Article
Publication date: 28 October 2014

Alexander Zemliak

The purpose of this paper is to define the process of analog circuit optimization on the basis of the control theory application. This approach produces many different…

Abstract

Purpose

The purpose of this paper is to define the process of analog circuit optimization on the basis of the control theory application. This approach produces many different strategies of optimization and determines the problem of searching of the best strategy in sense of minimal computer time. The determining of the best strategy of optimization and a searching of possible structure of this strategy with a minimal computer time is a principal aim of this work.

Design/methodology/approach

Different kinds of strategies for circuit optimization have been evaluated from the point of view of operations’ number. The generalized methodology for the optimization of analog circuit was formulated by means of the optimum control theory. The main equations for this methodology were elaborated. These equations include the special control functions that are introduced artificially. This approach generalizes the problem and generates an infinite number of different strategies of optimization. A problem of construction of the best algorithm of optimization is defined as a typical problem of the control theory. Numerical results show the possibility of application of this approach for optimization of electronic circuits and demonstrate the efficiency and perspective of the proposed methodology.

Findings

Examples show that the better optimization strategies that are appeared in limits of developed approach have a significant time gain with respect to the traditional strategy. The time gain increases when the size and the complexity of the optimized circuit are increasing. An additional acceleration effect was used to improve the properties of presented optimization process.

Originality/value

The obtained results show the perspectives of new approach for circuit optimization. A large set of various strategies of circuit optimization serves as a basis for searching the better strategies with a minimum computer time. The gain in processor time for the best strategy reaches till several thousands in comparison with traditional approach.

Details

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, vol. 33 no. 6
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 2 January 2018

Alexander Zemliak

This paper aims to propose a new approach on the problem of circuit optimisation by using the generalised optimisation methodology presented earlier. This approach is…

Abstract

Purpose

This paper aims to propose a new approach on the problem of circuit optimisation by using the generalised optimisation methodology presented earlier. This approach is focused on the application of the maximum principle of Pontryagin for searching the best structure of a control vector providing the minimum central processing unit (CPU) time.

Design/methodology/approach

The process of circuit optimisation is defined mathematically as a controllable dynamical system with a control vector that changes the internal structure of the equations of the optimisation procedure. In this case, a well-known maximum principle of Pontryagin is the best theoretical approach for finding of the optimum structure of control vector. A practical approach for the realisation of the maximum principle is based on the analysis of the behaviour of a Hamiltonian for various strategies of optimisation and provides the possibility to find the optimum points of switching for the control vector.

Findings

It is shown that in spite of the fact that the maximum principle is not a sufficient condition for obtaining the global minimum for the non-linear problem, the decision can be obtained in the form of local minima. These local minima provide rather a low value of the CPU time. Numerical results were obtained for both a two-dimensional case and an N-dimensional case.

Originality/value

The possibility of the use of the maximum principle of Pontryagin to a problem of circuit optimisation is analysed systematically for the first time. The important result is the theoretical justification of formerly discovered effect of acceleration of the process of circuit optimisation.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 37 no. 1
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 28 February 2020

Alexander Zemliak and Jorge Espinosa-Garcia

In this paper, on the basis of a previously developed approach to circuit optimization, the main element of which is the control vector that changes the form of the basic…

Abstract

Purpose

In this paper, on the basis of a previously developed approach to circuit optimization, the main element of which is the control vector that changes the form of the basic equations, the structure of the control vector is determined, which minimizes CPU time.

Design/methodology/approach

The circuit optimization process is defined as a controlled dynamic system with a special control vector. This vector serves as the main tool for generalizing the problem of circuit optimization and produces a huge number of different optimization strategies. The task of finding the best optimization strategy that minimizes processor time can be formulated. There is a need to find the optimal structure of the control vector that minimizes processor time. A special function, which is a combination of the Lyapunov function of the optimization process and its time derivative, was proposed to predict the optimal structure of the control vector. The found optimal positions of the switching points of the control vector give a large gain in CPU time in comparison with the traditional approach.

Findings

The optimal positions of the switching points of the components of the control vector were calculated. They minimize processor time. Numerical results are obtained for various circuits.

Originality/value

The Lyapunov function, which is one of the main characteristics of any dynamic system, is used to determine the optimal structure of the control vector, which minimizes the time of the circuit optimization process.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering , vol. 39 no. 3
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 28 November 2018

M.A. Mushahhid Majeed and Sreehari Rao Patri

This paper aims to resolve the sizing issues of analog circuit design by using proposed metaheuristic optimization algorithm.

Abstract

Purpose

This paper aims to resolve the sizing issues of analog circuit design by using proposed metaheuristic optimization algorithm.

Design/methodology/approach

The hybridization of whale optimization algorithm and modified gray wolf optimization (WOA-mGWO) algorithm is proposed, and the same is applied for the automated design of analog circuits.

Findings

The proposed hybrid WOA-mGWO algorithm demonstrates better performance in terms of convergence rates and average fitness of the function after testing it with 23 classical benchmark functions. Moreover, a rigorous performance evaluation is done with 20 independent runs using Wilcoxon rank-sum test.

Practical implications

For evaluating the performance of the proposed algorithm, a conventional two-stage operational amplifier is considered. The aspect ratios calculated by simulating the algorithm in MATLAB are later used to design the operational amplifier in Cadence environment using 180nm CMOS standard process.

Originality/value

The hybrid WOA-mGWO algorithm is tailored to improve the exploration ability of the algorithm by combining the abilities of two metaheristic algorithms, i.e. whale optimization algorithm and modified gray wolf optimization algorithm. To build further credence and to prove its profound existence in the latest state of the art, a statistical study is also conducted over 20 independent runs, for the robustness of the proposed algorithm, resulting in best, mean and worst solutions for analog IC sizing problem. A comparison of the best solution with other significant sizing tools proving the efficiency of hybrid WOA-mGWO algorithm is also provided. Montecarlo simulation and corner analysis are also performed to validate the endurance of the design.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 38 no. 1
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 2 August 2011

Franciszek Balik

The purpose of this paper is to present a new method of optimization of electronic integrated circuits (IC) with imbedded passive modules (PM). The reported method…

Abstract

Purpose

The purpose of this paper is to present a new method of optimization of electronic integrated circuits (IC) with imbedded passive modules (PM). The reported method constitutes an attempt to streamline the optimization process in the AC electrical model stage of the RF Microsystems design.

Design/methodology/approach

In this method, the PM are described in symbolic form while the IC blocks remain described numerically. Whole PM can be represented as some sequence of expressions containing crucial model parameters, nominal and parasitic, which are first precompiled and next, merged automatically with the main program.

Findings

The input data can be updated online according to the user's desiderata. Further, the system offers the possibility to optimize PM in diverse circumstances as well as using different technologies, and including parasitic effects.

Originality/value

Usage of the semi‐symbolic method for IC with embedded PM optimization based on large‐change sensitivity AC analysis method, which appears to be a very efficient and flexible approach to solving such problems.

Details

Microelectronics International, vol. 28 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 8 May 2018

Behnam Ghavami

Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical…

Abstract

Purpose

Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.

Design/methodology/approach

In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.

Findings

Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.

Originality/value

The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 37 no. 3
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 3 May 2013

Miguel Ángel San Pablo Juárez, Alexander Zemliak and Eduardo Ríos Silva

This work seeks to present the theoretical study considerations and the characteristics of a general design methodology in optimal time for electronic systems using…

Abstract

Purpose

This work seeks to present the theoretical study considerations and the characteristics of a general design methodology in optimal time for electronic systems using numerical methods and optimal control theory. Through this, the design problem of a system is formulated in terms of optimal control in minimal time.

Design/methodology/approach

This general design methodology includes the traditional design strategy (TDS), and the modified traditional design strategy (MTDS), where the model of the system is part of the optimization procedure but an objective function of the optimization process is constructed such as includes the traditional objective function and some penalty functions that feign the model of the system. Many special control functions are introduced artificially to generalize the methodology and produce several design trajectories for the same optimization process – the first and final trajectories correspond to TDS and MTDS, respectively. The combination of these trajectories produce an infinite number of design strategies, some of these are quasi‐optimal in time and only one is optimal in time.

Findings

Qualitative and numeric results of this iterative process are generated in a personal computer in a C++ language elaborated with a visual C++ graphic user interface. An algorithm is constructed to form an optimal in time design strategy switching from a MTDS subset to a TDS subset. Results of measured times are analyzed, showing that there is a control input U, such that the objective function is minimized in a minimum time.

Originality/value

These ideas are proposed using method of gradient optimization and special acceleration effect.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 32 no. 3
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 1 March 1992

M. Pavšek, D. Belavič, U. Kunaver and M. Hrovat

The design of temperature‐compensated quartz crystal oscillators (TCXOs) in thick film hybrid technology is described. TCXOs controlled by varicap diodes are usually…

Abstract

The design of temperature‐compensated quartz crystal oscillators (TCXOs) in thick film hybrid technology is described. TCXOs controlled by varicap diodes are usually realised with discrete NTC thermistors and resistors. Data obtained by precision measurements of voltages on varicap diodes for the same oscillator frequencies over the operating temperature range are used for calculating values of the NTC thermistors and resistors. In most cases these values cannot be found in the Renard scale, with the result that manipulation or ‘juggling’ of values is necessary. The realisation of temperature‐compensating circuits in thick film technology has certain advantages, such as miniaturisation, better characteristics at high frequencies and in particular the possibility to trim thick film resistors and NTC thermistors to values calculated for each oscillator. The method of realisation of TCXOs in thick film hybrid technology was developed and verified on prototypes. The compensation curves were obtained by measuring compensation voltages for each oscillator over the operating temperature range from — 20°C to 70°C. From these data the values of resistors and NTC thermistors were calculated. A computer program was used to minimise frequency instability error as a function of six parameters (resistance). The frequency stability (Δf/f) of TCXOs obtained was better than ±2 ppm.

Details

Microelectronics International, vol. 9 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 14 August 2020

Vaithiyanathan D., Megha Singh Kurmi, Alok Kumar Mishra and Britto Pari J.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high…

Abstract

Purpose

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

Design/methodology/approach

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

Findings

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

Originality/value

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Details

World Journal of Engineering, vol. 17 no. 6
Type: Research Article
ISSN: 1708-5284

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Article
Publication date: 5 September 2016

M. Amin Sabet and Behnam Ghavami

With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand…

Abstract

Purpose

With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation.

Design/methodology/approach

In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated.

Findings

Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime.

Originality/value

The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 35 no. 5
Type: Research Article
ISSN: 0332-1649

Keywords

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