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Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier’s performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure.

The multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs.

Exhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications.

The area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved.

This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.

The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.

Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.

The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs).

To design this cell, the capacitive threshold logic (CTL) has been used.

To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others.

This cell significantly reduces the number of transistors and only consists of NOT gates.

The purpose of this paper is the selection and arrangement of turbochargers set for internal combustion engine which could keep engine power in an altitude of up to 12.2 km above sea level.

In the current research, the target engine, a one-dimensional four-stroke 1,600 cc piston engine has been simulated and the manufacturer’ results have been validated. Depending on engine size, three proper types of Garret turbochargers GT30, GT25 and GT20 were selected for this engine. Then, the engine and a combination of two turbochargers have been modeled one-dimensionally. A control system was used for regulation of different pressure ratios between the two turbochargers.

The parametric analysis shows that using the combination of GT20, GT30 turbochargers with a properly controlled pressure ratio leads to a constant output power with little changes at different altitudes which enable achieving an altitude of 12.2 km for the target engine.

Adaptation of the internal combustion engine with a twin turbocharger using one-dimensional modeling.

The one-dimensional analysis provided an overall picture of the effective performance of turbochargers functioning in different altitudes and loads. It presents a new method for adopting of turbochargers set with internal combustion engines for propulsion medium-altitude aircraft.

This paper aims to implement a novel design of approximate comparator which can be suitable for image processing applications.

Here, the N-bit approximate comparator is implemented by taking reference of N as 2-, 4- and 8-bit. The design analyses the fractional change in error to bit in several bit formats. The final implementation of approximate comparator design application compares the structural similarity index, colour test and extraction of an image to the results.

The novel approximate comparator was designed using 2-, 4- and 8-bit to explore N-bit comparator expressions. The implementation, computations, evaluation of errors, applications and the design constraints were executed using Python and Synopsys, respectively. The computations, evaluation of errors, applications and the design constraints were executed using Python and Synopsys, respectively.

This paper presents the N-bit accurate and approximate comparator which is novel over the existing design of comparators.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms but most of them are not optimized enough. This paper aims to demonstrate QCA inherent capabilities that can facilitate the design of many important gates such as the XOR gate and multiplexer (MUX) without following any Boolean function to get an optimum design in terms of complexity and delay.

In this paper, a novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell. The proposed RAM cells are the lowest cost required compared with different counterparts. The presented RAM cells used a new approach that follows the new suggested block diagram. The presented circuits are simulated and tested with QCADesigner and QCAPro tools.

The comparison of the proposed circuits with the previously reported in the literature show noticeable improvements in speed, area, and the number of cells. The cost function analysis results for the proposed RAM cells show significant improvement compared to older circuits.

A novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell.

The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors.

Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs.

The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased.

The proposed half subtractor and full subtractor show better performance over the existing subtractors.

The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.

To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.

The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA.

As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator.

Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects.

A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.