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This study aims to examine how corruption influences the voluntary disclosure of corporate governance (CG)-related information by developed country multinationals (DC-MNEs) and emerging market multinationals (EM-MNEs) investing in six Latin American countries.

The study uses information from 300 MNEs included in the 2018 ranking of the 500 Largest Latin American companies (America Economía, 2018). Each MNE’s final annual report for the financial year ending 2018 was examined and coded to obtain the corporate governance disclosure index. Fractional probit regression was applied to test the hypotheses of the research.

DC-MNEs disclose more CG-related information in corrupt environments than EM-MNEs. This differentiated behavior occurs because DC-MNEs face higher legitimacy pressures in corrupt environments than EM-MNEs and because EM-MNEs are more experienced than DC-MNEs in dealing with such corrupt environments.

While both EM-MNEs and DC-MNEs need to continue investing in corrupt countries to grow, they need to disclose CG-related information as a strategic tool to manage the legitimacy issues triggered by corruption in the markets they operate.

Despite corruption being pervasive in emerging markets, its implications for firms’ strategic behaviors are still under-researched. This paper extends the scope of corporate governance and international business fields by studying how MNEs respond to relevant dimensions of the macro environment. This research shows that voluntary disclosure of CG-related information is a strategic response of the MNEs to gain legitimacy in corrupt environments.

This paper aims to propose a novel integrated control method (ICM) for high-power-density non-inverting interleaved buck-boost DC-DC converter. To achieve high power conversion by conventional single phase DC-DC converter, inductor value must be increased. This converter is not suitable for industrial and high-power applications as large inductor value will increase the inductor current ripple. Thus, two-phase non-inverting interleaved buck-boost DC-DC converter is proposed.

The proposed ICM approach is based on the theory of integrated dynamic modeling of continuous conduction mode (CCM), discontinuous conduction mode and synchronizing parallel operation mode. In addition, it involves the output voltage controller with inner current loop (inductor current controller) to make a fair balancing between two stages. To ensure fast transient performance, proposed digital ICM is implemented based on a TMS320F28335 digital signal microprocessor.

The results verify the effectiveness of the proposed ICM algorithm to achieve high voltage regulating (under 0.01 per cent), very low inductor current ripple (for boost is 1.96 per cent, for buck is 1.1) and fair input current balance between two stages (unbalancing current less than 0.5A).

The proposed new ICM design procedure is developed satisfactorily to ensure fast transient response even under high load variation and the solving R right-half-plane HP zeros of the CCM. In addition, the proposed method can equally divide the input current of stages and stable different parallel operation modes with large input voltage variations.

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

To derive an analytical model for a dc‐ac‐dc parallel resonant converter operating in lagging power factor mode based on the steady‐state operation conditions and considering the effects of a high‐frequency transformer.

A range of published works relevant to dc‐ac‐dc converters and their control methods based on pulse‐width‐modulation technique are evaluated and their limitations in output measurement of higher output voltage converters are indicated. The circuit diagram of the converter is described and the general mathematical model of the system is obtained by deriving and combining the mathematical models of the different converter blocks existing in the system. The derived mathematical model is used to study the steady‐state and transient performance of the converter. The deriving procedure of the analytical model for a parallel resonant converter is extensively given and the analytical model obtained is verified by simulation results achieved using MATLAB/SIMULINK and the program written by the authors.

The paper suggests an analytical model for dc‐ac‐dc parallel resonant converters. The model can be used in the output voltage estimation of a converter in terms of its phase‐shift angle and the dc‐link voltage.

The resources in the library of the authors' university and also the English resources relative to dc‐ac‐dc converters reachable through the internet were researched.

The analytical model suggested can be used in estimating the output voltage of the converters used in high‐voltage applications or where there are difficulties in employing sensors in measurement of the output voltage due to high price or implementation problems.

The originality of the paper is to present an analytical model for dc‐ac‐dc parallel resonant converters. Using this model makes it possible to estimate the output voltage of the converter using the dc‐link voltage and the phase‐shift angle. The proposed model provides researchers to regulate the output voltage of the converters using feed‐forward control technique.

Control-signal-to-output-voltage transfer function of the conventional boost converter has at least one right-half plane zero (RHPZ) in the continuous conduction mode which can restrict the open-loop bandwidth of the converter. This problem can complicate the control design for the load voltage regulation and conversely, impact on the stability of the closed-loop system. To remove this positive zero and improve the dynamic performance, this paper aims to suggest a novel boost topology with a step-up voltage gain by developing the circuit diagram of a conventional boost converter.

Using a transformer, two different pathways are provided for a classical boost circuit. Hence, the effect of the RHPZ can be easily canceled and the voltage gain can be enhanced which provides conditions for achieving a smaller working duty cycle and reducing the voltage stress of the power switch. Using this technique makes it possible to achieve a good dynamic response compared to the classical boost converter.

The observations show that the phase margin of the proposed boost converter can be adequately improved, its bandwidth is largely increased, due to its minimum-phase structure through RHPZ cancellation. It is suitable for fast dynamic response applications such as micro-inverters and fuel cells.

The introduced method is analytically studied via determining the state-space model and necessary criteria are obtained to achieve a minimum-phase structure. Practical observations of a constructed prototype for the voltage conversion from 24 V to 100 V and various load conditions are shown.

The aim of the paper is the fine‐tuning of proportional integral derivative (PID) controllers under model parameter uncertainties (noise).

The fine‐tuning of PID controllers achieved using the Taguchi method following the steps given: selection of the control factors of the PID with their levels; identification of the noise factors that cause undesirable variation on the quality characteristic of PID; design of the matrix experiment and definition of the data analysis procedure; analysis of the data; decision regarding optimum settings of the control parameters and predictions of the performance at optimum levels of control factors; calculation of the expected cost savings under optimum condition; and confirmation of experimental results.

An example of the proposed method is presented and demonstrates that given certain performance criteria, the Taguchi method can indeed provide sub‐optimal values for fine PID tuning in the presence of model parameter uncertainties (noise). The contribution of each factor to the variation of the mean and the variability of error is also calculated. The expected cost savings for PID under optimum condition are calculated. The confirmation experiments are conducted on a real PID controller.

As a further research it is proposed the contiguous fine‐tuning of PID controllers under a number of a variant controllable models (noise).

The enhancement of PID controllers by Taguchi method is proposed with the form of a hardware mechanism. This mechanism will be incorporated in the PID controller and automatically regulate the PID parameters reducing the noise influence.

Application of Taguchi method in the scientific field of automation control.

This paper aims to review comprehensively the different voltage-boosting techniques and classifies according to their voltage gain, stress on the semiconductor devices, count of the total components and their prominent features. Hence, the focus is on non-isolated step-up converters. The converters categorized are analyzed according to their category with graphical representation.

Many converters have been reported in recent years in the literature to meet our power requirements from mill watts to megawatts. Fast growth in the generation of renewable energy in the past few years has promoted the selection of suitable converters that directly impact the behaviour of renewable energy systems. Step-up converters are a fast-emerging switching power converter in various power supply units. Researchers are more attracted to the derivation of novel topology with a high voltage gain, low voltage and current stress, high efficiency, low cost, etc.

A comparative study is done on critical metrics such as voltage gain, switch voltage stress and component count. Besides, the converters are also summarized based on their advantages and disadvantages. Furthermore, the areas that need to be explored in this field are identified and presented.

Types of analysis usually performed in dc converter and their needs with the areas need to be focused are not yet completely reviewed in most of the articles. This paper gives an eyesight on these topics. This paper will guide the researchers to derive and suggest a suitable topology for the chosen application. Moreover, it can be used as a handbook for studying the various topologies with their shortfalls, which will provide a way for researchers to focus.

Switching power converters for photovoltaic (PV) applications with high gain are rapidly expanding. To obtain better voltage gain, low switch stress, low ripple and cost-effective converters, researchers are developing several topologies.

It was decided to use the particle swarm optimization approach for this system in order to compute the precise PI controller gain parameters under steady state and dynamic changing circumstances. A high-gain q- ZS boost converter is used as an intermittent converter between a PV and brushless direct current (BLDC) motor to attain maximum power point tracking, which also reduces the torque ripples. A MATLAB/Simulink environment has been used to build and test the positive output quadratic boost high gain converters (PQBHGC)-1, PQBHGC-8, PQBHGC-4 and PQBHGC-3 topologies to analyse their effectiveness in PV-driven BLDC motor applications. The simulation results show that the PQBHGC-3 topology is effective in comparison with other HG cell DC–DC converters in terms of efficiency, reduced ripples, etc. which is most suitable for PV-driven BLDC applications.

The simulation results have showed that the PQBHGC-3 gives better performance with minimum voltage ripple of 2V and current ripple of 0.4A which eventually reduces the ripples in the torque in a BLDC motor. Also, the efficiency for the suggested PQBHGC-3 for PV-based BLDC applications is the best with 99%.

This study is the first of its kind comparing the different topologies of PQBHGC-1, PQBHGC-8, PQBHGC-4 and PQBHGC-3 topologies to analyse their effectiveness in PV-driven BLDC motor applications. This study suggests that the PQBHGC-3 topology is most suitable in PV-driven BLDC applications.

The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.

An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm².

Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.

The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

To model the differential dc gain, base resistance, and current voltage performance of 4H‐Silicon Carbide (SiC) bipolar junction transistors (BJT) operating at and above room temperature. Accurate modeling will result in improved process efficiency, interpretation of experimental data, and insight into device behavior.

The PISCES two dimensional device simulation program is used to allow for modeling the behavior of 4H‐SiC BJT. The physical material parameters in PISCES such as carrier's mobility and lifetime, temperature dependent bandgap, and the density of states are modified to accurately represent 4H‐SiC. The simulation results are compared with the measured experimental data obtained by others. The comparisons made with the experimental data are for two different devices that are of interest in power electronics and RF applications.

The simulation results predict a dc current gain of about 25 for power device and a gain of about 20 for RF device in agreement with the experimental data. The comparisons confirm the accuracy of the modeling employed.

The simulated current‐voltage characteristics indicate that higher gain may be achieved for 4H‐SiC transistors if the leakage current is reduced.

The simulation work discussed in this paper complements the current research in the design and characterization of 4H‐SiC bipolar transistors. The model presented will aid in interpreting experimental data at a wide range of temperatures.

This paper reports on a new model that provides insight into the device behavior and shows the trend in the dc gain performance important for the design and optimization of 4H‐SiC bipolar transistors operating at or above the room temperature.