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In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Power‐electronic systems have been playing a significant role in the integration of large‐scale wind turbines into power systems due to the fact that during the past three decades power‐electronic technology has experienced a dramatic evolution. This second part of the paper aims to focus on a comprehensive survey of power converters and their associated control systems for high‐power wind energy generation applications.

Advanced control strategies, i.e. field‐oriented vector control and direct power control, are initially reviewed for wind‐turbine driven doubly fed induction generator (DFIG) systems. Various topologies of power converters, comprising back‐to‐back (BTB) connected two‐ and multi‐level voltage source converters (VSCs), BTB current source converters (CSCs) and matrix converters, are identified for high‐power wind‐turbine driven PMSG systems, with their respective features and challenges outlined. Finally, several control issues, viz., basic control targets, active damping control and sensorless control schemes, are elaborated for the machine‐ and grid‐side converters of PMSG wind generation systems.

For high‐power PMSG‐based wind turbines ranging from 3 MW to 5 MW, parallel‐connected 2‐level LV BTB VSCs are the most cost‐effective converter topology with mature commercial products, particularly for dual 3‐phase stator‐winding PMSG generation systems. For higher‐capacity wind‐turbine driven PMSGs rated from 5 MW to 10 MW, medium voltage multi‐level converters, such as 5‐level regenerative CHB, 3‐ and 4‐level FC BTB VSC, and 3‐level BTB VSC, are preferred. Among them, 3‐level BTB NPC topology is the favorite with well‐proven technology and industrial applications, which can also be extensively applicable with open‐end winding and dual stator‐winding PMSGs so as to create even higher voltage/power wind generation systems. Sensorless control algorithms based on fundamental voltages/currents are suggested to be employed in the basic VC/DPC schemes for enhancing the robustness in the entire PMSG‐based wind power generation system, due to that the problems related with electromagnetic interferences in the position signals and the failures in the mechanical encoders can be avoided.

This second part of the paper for the first time systematically reviews the latest state of arts with regard to power converters and their associated advanced control strategies for high‐power wind energy generation applications. It summarizes a variety of converter topologies with pros and cons highlighted for different power ratings of wind turbines.

These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

Multilevel inverters become very popular in medium voltage applications owing to their inherent capability of reconciling stepped voltage waveform with reduced harmonic distortion and electromagnetic interference. They have several disadvantages like more number of switching devices required and devices with high voltage blocking and need additional dc sources count to engender particular voltage. So this paper aims to propose a novel tri-source symmetric cascaded multilevel inverter topology with reduced number of switching components and dc sources.

A novel multilevel inverter has been suggested in this study, offering minimal switch count in the conduction channel for the desired voltage level under symmetric and asymmetric configurations. This novel topology is optimized to prompt enormous output voltage levels by employing constant power switches count and/or dc sources of voltage. The topology claims its advantages in generating higher voltage levels with lesser number of voltage sources, gate drivers and dc voltage sources.

The consummation of the proposed arrangement is verified in Matlab/Simulink R2015b, and an experimental prototype for 7-level, 13-level, 21-level, 29-level, 25-level and 49-level operation modes is constructed to validate the simulation results.

The proposed topology operated with six new algorithms for asymmetrical configuration to propel increased number of voltage levels with reduced power components.

The aim of this paper is to improve and adapt cascaded multilevel converters for electric vehicles (EVs) to have all the advantages of these converters and to eliminate its limitation in the use of EVs applications. Specifically, the purpose is to use only a single power source (battery pack, fuel cell, etc.) and to generate a higher power‐quality than regular multilevel converters.

This paper is based in a cascaded multilevel converter conformed by two 3‐level inverters connected in series. The voltage sources of the auxiliary inverter were replaced by floating capacitors which work as active filters, reducing the power sources to one. The floating capacitor voltages were controlled by a PI controller that adjusts the modulation index (m) to obtain a zero average power in the auxiliary inverters, and a predictive control selects the optimal redundant state to reduce the error and balance all the capacitor voltages. As the modulation index is determined by the PI controller, the output voltage magnitude must be controlled by a variable voltage source (e.g. buck‐boost chopper). Additionally, the converter works with new optimal voltage asymmetries to obtain higher power quality and capacitor control stability.

The proposed converter uses a topology that conventionally generates 9‐levels of voltage, but with the proposed asymmetry is as generate 11‐levels. Also, the auxiliary power sources were eliminated.

The proposed solution has a limited dynamic response due to the variation rate of the capacitor voltage, which is limited by the load current and the capacitance. However, the dynamic response and control stability is satisfactory for EVs applications.

The paper presents a new control to manage the floating capacitor voltages and uses new voltage asymmetries in cascaded multilevel converters.

The main purpose of this paper is to select appropriate voltage vectors in the switching techniques and, by selecting the proper voltage vectors, be able to achieve a DC link with the same outputs and a symmetric multi-level inverter.

The proposed structure, a two-stage DC–AC symmetric multi-level inverter with modified Model Predictive Control (MMPC) method, is presented for Photovoltaic (PV) applications. The voltage of DC-link capacitors of the boost converter is controlled by MMPC control method to select appropriate switching vectors for the multi-level inverter. The proposed structure is provided for single-phase power system, which increases 65 V input voltage to 220 V/50 Hz output voltage, with 400 V DC link. Simulation results of proposed structure with MMPC method are carried out by PSCAD/EMTDC software.

Based on the proposed structure and control method, total harmonic distortion (THD) reduces, which leads to lower power losses and higher circuit reliability. In addition, reducing the number of active switches in current path causes to lower voltage stress on the switches, lower PV leakage current and higher overall efficiency.

In the proposed structure, a new control method is presented that can make a symmetric five-level voltage with lower THD by selecting proper switching for PV applications.

The purpose of this paper is to focus on conducting accelerated life tests on aluminium electrolytic capacitors under accelerated temperature and voltage stress to study the effect of applied voltage and ambient temperature on the capacitor, its degradation over time, failure data collection, analysis and then modelling the failure times. Principles of DOE are used for studying the effect of temperature and voltage.

Life tests are conducted at three levels of temperature and applied voltage and the life of capacitor is ascertained at each treatment level. Life variation with voltage and temperature is studied to gain an insight as to how these factors affect the lifetime of the capacitor. The interaction effect of temperature and voltage on capacitor life is also established.

The life of the capacitor decreases exponentially with temperature and voltage at all the three factor levels. Ambient temperature, applied voltage and their interaction effect significantly affects the life of the capacitor. Applied voltage has the greatest effect followed by ambient temperature and then their interaction effect. Life of the capacitor has been estimated as 4,206 hrs when only voltage is taken as the accelerated stress using Inverse Power Law and as 4,003 hrs when both temperature and voltage are taken as accelerating stress using combination model.

This work consider only decrease in capacitance as the failure criterion. However, as a future scope, it is proposed that test may be conducted by taking into consideration not only the decrease in capacitance as the failure criteria but by monitoring all the performance parameters of the capacitor. This would give a more realistic assessment of life as it is possible that capacitor may have failed much before it reached the lower threshold capacitance value.

This work has lots of practical implications. It shows how DOE approach can be used for ALT data analysis and identification and effect of critical stresses acting on capacitors in real practice. Most critical types of stresses affecting the reliability can thus be controlled to ensure better performance. Product manufactures as well as users will be benefited by such findings. The paper has also illustrated how failure data can generated by degradation analysis using life test data collection at discrete intervals.

The methodology presents an alternative non traditional approach of accelerated life testing, which does not require continuous monitoring of test items. This only requires intermittent monitoring which reduces the need of test resources. Though the degradation study itself is not new but using degradation study for ALT data generation is new. This approach may considerably reduce the test duration and resources used for ALT. DOE approach gives more tangible result to study the effect of various variables on the dependent variable. As DOE approach uses a fractional factorial design, it can be very helpful to conduct life tests with minimum number of test units (only a fraction of full factorial test units). This will considerably reduce the test duration, resources requirement for testing, easier but accurate data analysis, and faster product development, especially when ALT is to be conducted at several stresses simultaneously.

Multilevel inverter (MLI) is an established design approach for inverter applications in medium-voltage and high-voltage range of applications. An asymmetric design synthesizes multiple DC input voltage sources of unequal magnitudes to generate a high-quality staircase sinewave comprising a large number of steps or levels. However, the implications of using sources of unequal magnitudes results in the requirements of a large variety of inverter switches and higher magnitudes of the total blocking voltage (TBV) rating of the inverter, which increase the cost. The purpose of this study is to present a solution based on algorithms for establishing DC source magnitudes and other design parameters.

The approach used in this study is to develop algorithms that bring an asymmetric cascaded MLI (ACMLI) design close to symmetric design. This approach then reduces the variety of switch ratings and minimizes the TBV of the inverter. Thus, the benefits of both asymmetric design (generation of a large number of voltage levels in the output waveform) and symmetric design (modularity) are achieved. The proposed algorithms can be applied to a number of ACMLI topologies, including classical cascaded H-bridge (CHB). The effectiveness of the proposed algorithms is validated by simulation in Matlab-Simulink and experimental setup.

Two new algorithms are proposed that reduce the number of variety of switches to just three. The variety can further be reduced to two under a specified condition. The algorithms are compared with the existing ones, and the results are promising in minimizing the TBV rating of the inverter, which results in cost reduction as well. For a specific case of four CHBs, the proposed Algorithm-1 produced 27% and Algorithm-2 produced 53% higher levels. Moreover, the presented algorithms produced minimum values of the TBV and resulted in minimum cost of inverter.

The proposed algorithms are novel in structure and have achieved the targeted values of minimized switch variety and reduced TBV ratings. Due to less variety, the inverter achieves a near symmetric design, which enables to attain the added advantages of modularity and reduced difference of power sharing among the DC sources.

The purpose of this paper is to describe the control and regulation of input DC voltages of nine‐level neutral point clamping (NPC) voltage source inverter (VSI).

The analysis and simulation of a cascade made up of three‐phase five‐level PWM rectifier‐nine levels NPC VSI are treated. This cascade is used to feed a permanent magnet synchronous machine (PMSM) drive. First, the five‐level PWM rectifier is presented. Then a topology of nine‐level NPC VSI and the associated PWM control strategy are described. In order to discard the problem of DC link voltage fluctuations, a clamping bridge with a PI regulation has been added to the cascade. Then a field‐oriented control strategy has been implemented in the PMSM.

The obtained results are full of promise to use the inverter in high voltage and great power applications such as electric naval propulsion systems.

The application of the proposed feedback control algorithm to the studied cascade offers the possibility of stabilizing the DC voltages. The studied cascade absorbs network currents with low‐harmonic content and unity power factor. In all, the instability problems associated with use of multilevel inverters are solved.

The purpose of this paper is to design a cascaded Multilevel inverter with reduce number of switches for high power applications. This paper came up with an innovative three-phase multilevel inverter (MLI) topology, which is a cascaded structure based on classical three-legged voltage source inverter (VSI) bridges as an individual module. The prominent advantage of this topology is that it requires only one direct current (DC) link system. The main characteristic of it is that a higher number of voltage levels can be achieved with considerably a smaller number of semiconductor switches, which improves the reliability, power quality, cost and size of the system significantly.

The individual modules are cascaded through three-phase transformers to provide higher voltage at the output with the higher number of voltage levels. In this work, the phase-shifted pulse width modulation technique is implemented to verify the result.

The proposed topology is compared with three-phase cascaded H-bridge MLI (CHB-MLI) and a modified CHB-MLI topology and found better in many aspects. The proposed MLI can produce a higher number of voltage levels with fewer semiconductor switches and associated triggering circuitry. As the device count in the proposed MLI is less compared to other MLI discussed, it tends to have less switching and conduction loss which increases the efficiency and reliability. As the number of level increases, the voltage profile and the total harmonic distortion of the proposed MLI improves.

This is a transformer-based modular cascaded MLI, which is based on classical VSI bridges. Here in this topology, a single module provides all three phases. So, a single string of cascaded modules is enough for three-phase multilevel voltage generation.