To read this content please select one of the options below:

A new tri-source symmetric cascaded multilevel inverter topology with reduced power components

Jayarama Pradeep (Department of Electrical and Electronics Engineering, St. Joseph’s College of Engineering, Chennai, India)
Krishnakumar Vengadakrishnan (Department of Electrical and Electronics Engineering, St. Joseph’s College of Engineering, Chennai, India)
Anbarasan Palani (Department of Electrical and Electronics Engineering, St. Joseph’s College of Engineering, Chennai, India)
Thamizharasan Sandirasegarane (SK Powercon Fabricators, Puducherry, India)

Circuit World

ISSN: 0305-6120

Article publication date: 28 February 2022

Issue publication date: 8 November 2023

84

Abstract

Purpose

Multilevel inverters become very popular in medium voltage applications owing to their inherent capability of reconciling stepped voltage waveform with reduced harmonic distortion and electromagnetic interference. They have several disadvantages like more number of switching devices required and devices with high voltage blocking and need additional dc sources count to engender particular voltage. So this paper aims to propose a novel tri-source symmetric cascaded multilevel inverter topology with reduced number of switching components and dc sources.

Design/methodology/approach

A novel multilevel inverter has been suggested in this study, offering minimal switch count in the conduction channel for the desired voltage level under symmetric and asymmetric configurations. This novel topology is optimized to prompt enormous output voltage levels by employing constant power switches count and/or dc sources of voltage. The topology claims its advantages in generating higher voltage levels with lesser number of voltage sources, gate drivers and dc voltage sources.

Findings

The consummation of the proposed arrangement is verified in Matlab/Simulink R2015b, and an experimental prototype for 7-level, 13-level, 21-level, 29-level, 25-level and 49-level operation modes is constructed to validate the simulation results.

Originality/value

The proposed topology operated with six new algorithms for asymmetrical configuration to propel increased number of voltage levels with reduced power components.

Keywords

Citation

Pradeep, J., Vengadakrishnan, K., Palani, A. and Sandirasegarane, T. (2023), "A new tri-source symmetric cascaded multilevel inverter topology with reduced power components", Circuit World, Vol. 49 No. 4, pp. 431-444. https://doi.org/10.1108/CW-06-2021-0184

Publisher

:

Emerald Publishing Limited

Copyright © 2022, Emerald Publishing Limited

Related articles