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The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).

First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.

In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.

Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.

This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

The aim of this work is to examine the Hopfield network for the field programmable gate array (FPGA) cell placement.

Implementation of an algorithm in FPGA circuits requires synthesis, placement and the routing of logic cells. The placement takes the longest time for computation. Therefore, an algorithm for a run‐time reconfigurable system can be chosen from among earlier prepared algorithms. This paper presents a Hopfield neural network for solving the placement problem. The Hopfield network was also used for processing units in a parallel placement. Hardware implementation of presented solutions could accelerate the FPGA placement by orders of magnitude in comparison with placers executed on traditional computers. Hardware accelerators could also be applied to the design of other VLSI circuits. The simulation results for the FPGA placement are presented.

The Hopfield network and parallel placement give comparable placements with the method using a simulated annealing algorithm. The parallel placement enables a decrease in total number of neurons and neuron connections which are necessary for simultaneous placement of all cells in a circuit.

This work provides a starting‐point for further research under hardware realization of the cell placement by using the Hopfield network. The presented solutions can be used for FPGA, gate array, sea‐of‐gates circuits and standard cell circuits with the same size cells.

The Hopfield network is used for placement in real circuits, in which nets contain multiple terminals, and for processing units in a parallel placement.

The purpose of this paper is to present a fixed‐point implementation of a complete direct torque control (DTC) algorithm connected with a rotor speed estimation algorithm for the induction motor drive, using field‐programmable gate array (FPGA).

The parallel processing approach is described, which requires a decomposition of the control and estimation algorithms for the converter‐fed induction motor to several tasks, realised in parallel. The advanced data processing techniques are described, like PIPELINE technique for data streams design, coordinate rotation digital computer algorithm for transformation of stator flux vector components from Cartesian to polar coordinates. Moreover, the method for the qualitative analysis of the full‐order state observer's sensitivity to the variations of the induction motor equivalent circuit parameters is presented.

It is shown that the developed FPGA‐based DTC structure enables designing an efficient application for the induction motor control. Owing to the high‐processing frequency, the digital FPGA‐based DTC application is similar in its features to the analogue realisation based on the comparators. Yet all the advantages of the digital structure, i.e. high flexibility, parameterization capability, etc. remain unchanged. Furthermore, FPGA is hardware realisation of a digital data processing algorithm; hence the reliability of the control system is improved.

The investigations are performed in the developing prototype setup, based on PXI‐1042 Industrial PC equipped with Xilinx Virtex‐II FPGA matrix, programmed with LabVIEW.

The experimental tests of the FPGA‐based implementation of the whole control structure of the sensorless DTC drive system are demonstrated. It is also shown, that the full‐order state observer with the speed adaptation loop is significantly sensitive to motor parameter variations in the low‐speed region, which must be taken into account while designing the adaptation algorithm for speed estimation in real application.

The paper's value lies in the overall, FPGA‐based design of the speed sensorless DTC structure for the induction motor including motor speed, torque and stator flux control loops, stator flux and rotor speed estimation.

These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

The purpose of this study was the use of embedded components technology and innovative concepts of the printed circuit board (PCB) for electronic modules containing field-programmable gate array (FPGA) devices with a large number of pins (e.g. Virtex 6, FF1156/RF1156 package, 1,156 pins).

In the multi-layered boards, embedded passive components that support FPGA device input/output (I/O), such as blocking capacitors and pull-up resistors, were used. These modules can be used in rapid design of electronic devices. In the study, the MC16T FaradFlex material was used for the inner capacitive layer. The Ohmega-Ply RCM 25 Ω/sq material was used to manufacture pull-up resistors for high-frequency pins. The embedded components have been connected to pins of the FPGA component by using plated-through holes for capacitors and blind vias for resistors. Also, a technique for a board-to-board joining, by using castellated terminations, is described.

The fully functional modules for assembly of the FPGA were manufactured. Achieved resistance of embedded micro resistors, as small as the smallest currently used surface-mount device components (01005), was below required tolerance of 10 per cent. Obtained tolerance of capacitors was less than 3 per cent. Use of embedded components allowed to replace the pull-up resistors and blocking capacitors and shortens the signal path from the I/O of the FPGA. Correct connection to the castellated terminations with a very small pitch was also obtained. This allows in further planned studies to create a full signal distribution system from the FPGA without the use of unreliable plug connectors in aviation and space technology.

This study developed and manufactured several innovative concepts of signal distribution from printed circuit boards. The signal distribution solutions were integrated with embedded components, which allowed for significant reduction in the signal path. This study allows us to build the target object that is the module for rapid design of the FPGA device. Usage of a pre-designed module would lessen the time needed to develop a FPGA-based device, as a significant part of the necessary work (mainly designing the signal and power fan-out) will already be done during the module development.

Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor.

A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library.

The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization.

Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.

Deep learning techniques are unavoidable in a variety of domains such as health care, computer vision, cyber-security and so on. These algorithms demand high data transfers but require bottlenecks in achieving the high speed and low latency synchronization while being implemented in the real hardware architectures. Though direct memory access controller (DMAC) has gained a brighter light of research for achieving bulk data transfers, existing direct memory access (DMA) systems continue to face the challenges of achieving high-speed communication. The purpose of this study is to develop an adaptive-configured DMA architecture for bulk data transfer with high throughput and less time-delayed computation.

The proposed methodology consists of a heterogeneous computing system integrated with specialized hardware and software. For the hardware, the authors propose an field programmable gate array (FPGA)-based DMAC, which transfers the data to the graphics processing unit (GPU) using PCI-Express. The workload characterization technique is designed using Python software and is implementable for the advanced risk machine Cortex architecture with a suitable communication interface. This module offloads the input streams of data to the FPGA and initiates the FPGA for the control flow of data to the GPU that can achieve efficient processing.

This paper presents an evaluation of a configurable workload-based DMA controller for collecting the data from the input devices and concurrently applying it to the GPU architecture, bypassing the hardware and software extraneous copies and bottlenecks via PCI Express. It also investigates the usage of adaptive DMA memory buffer allocation and workload characterization techniques. The proposed DMA architecture is compared with the other existing DMA architectures in which the performance of the proposed DMAC outperforms traditional DMA by achieving 96% throughput and 50% less latency synchronization.

The proposed gated recurrent unit has produced 95.6% accuracy in characterization of the workloads into heavy, medium and normal. The proposed model has outperformed the other algorithms and proves its strength for workload characterization.

The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model.

Numerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board.

With the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit.

Without any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.

The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.

An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.

FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm² of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.

The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

The proportional‐integral‐derivative (PID) controller has been a practical application in industry due to its simple architecture, being easily designed and its parameter tuning without complicated computation. However, the traditional PID controller usually needs some manual retuning before being used for practical application in industry. The purpose of this paper is to propose an auto‐tuning PID controller (ATPIDC) which can automatically tune the controller parameters based on the gradient descent method and the Lyapunov stability theorem. Finally, a field‐programmable gate array (FPGA) chip is adopted to implement the proposed ATPIDC scheme for possible low‐cost and high‐performance industrial applications, and it is applied to a DC servomotor to show its effectiveness.

To ensure the stability of the intelligent control system, a compensator usually should be designed. The most frequently used compensator is designed as a sliding‐mode control, which results in substantial chattering in the control effort. To tackle this problem, the proposed ATPIDC system is composed of a PID controller and a fuzzy compensator. The PID controller can automatically tune the gain factors of the controller gains based on the gradient descent method, and the fuzzy compensator is utilized to eliminate approximation error based on the Lyapunov stability theorem. The proposed fuzzy compensator not only can remove the chattering phenomena of conventional sliding‐mode control completely, but also can guarantee the stability of the closed‐loop system.

The proposed ATPIDC system is applied to a DC servomotor on a FPGA chip. The hardware implementation of the ATPIDC scheme is developed in a real‐time mode. Using the FPGA to implement, the ATPIDC system can achieve the characteristics of small size, fast execution speed and less memory. A comparison among the fuzzy sliding‐mode control, adaptive robust PID control and the proposed ATPIDC is made. Experimental results verify a better position tracking response can be achieved by the proposed ATPIDC method after control parameters training.

The proposed ATPIDC approach is interesting for the design of an intelligent control scheme. An on‐line parameter training methodology, using the gradient descent method and the Lyapunov stability theorem, is proposed to increase the learning capability. The experimental results verify the system stabilization, favorable tracking performance and no chattering phenomena can be achieved by using the proposed ATPIDC system. Also, the proposed ATPIDC methodology can be easily extended to other motors.