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An efficient method is shown to calculate the temperature distribution and the thermal coupling elements in integrated circuits. With that it is possible to treat circuits under nonisothermal conditions. The algorithm combines several methods of the three‐dimensional solution of the FOURIER equation to analyse real heat problems of integrated circuits in a short computation time. Some examples illustrate the application of the algorithm.

The transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More than Moore. The main problems in the development of 3-D IC are Joule heating and stress. The stresses and strains generated in 3-D ICs will affect the performance of electronic products, leading to various reliability issues. The intermetallic compound (IMC) joint materials and structures are the main factors affecting 3-D IC stress. The purpose of this paper is to optimize the design of the 3-D IC.

To optimize the design of 3-D IC, the numerical model of 3-D IC was established. The Taguchi experiment was designed to simulate the influence of IMC joint material, solder joint array and package size on 3-D IC stress.

The simulation results show that the solder joint array and IMC joint materials have great influence on the equivalent stress. Compared with the original design, the von Mises stress of the optimal design was reduced by 69.96 per cent, the signal-to-noise ratio (S/N) was increased by 10.46 dB and the fatigue life of the Sn-3.9Ag-0.6Cu solder joint was increased from 415 to 533 cycles, indicating that the reliability of the 3-D IC has been significantly improved.

It is necessary to study the material properties of the bonded structure since 3-D IC is a new packaging structure. Currently, there is no relevant research on the optimization design of solder joint array in 3-D IC. Therefore, the IMC joint material, the solder joint array, the chip thickness and the substrate thickness are selected as the control factors to analyze the influence of various factors on the 3-D IC stress and design. The orthogonal experiment is used to optimize the structure of the 3-D IC.

This study aims to present an optical alignment and compensation control of die bonder for chips containing through-silicon vias and develop three-dimensional integrated circuit stacked packaging for compact size and multifunction.

The machine vision, optical alignment method and sub-pixel technology in dynamic imaging condition are used. Through a comparison of reference image, the chip alignment calibration can improve machine accuracy and stability.

According to the experimental data and preliminary results of the analysis, accuracy can be achieved within the desired range, and the accuracy is much better than traditional die bonder equipment. The results help further research in die bonder for chips containing through-silicon vias.

In subsequent testing of the chip, the machine can simultaneously test multiple chips to save test time and increase productivity.

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs).

This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package.

This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package.

Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed.

The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board.

In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model.

The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

This paper aims to investigate Cu/SnAgCu/Cu transient liquid phase (TLP) bonding with different thicknesses for three-dimensional (3D) integrated circuit (IC).

This paper includes experiments and finite element simulation.

The growth rate of the intermetallic compound layer during TLP soldering was calculated to be 0.6 μm/s, and the small scallop-type morphology Cu₆Sn₅ grains can be observed. With the decrease in thickness in solder joint, the thickness of intermetallic compounds represents the same size and morphology, but the size of eutectic particles (Ag₃Sn, Cu₆Sn₅) in the matrix microstructure decrease obviously. It is found that with the increase in thickness, the tensile strength drops obviously. Based on finite element simulation, the smaller value of von Mises demonstrated that the more reliability of lead-free solder joints in 3D IC.

The Cu/SnAgCu/CuTLPbondingwithdifferentthicknessesfor3D IC was investigated.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

The purpose of this survey is to find a significant sample of reference resources for electrical engineering as they are presented in subject-specific LibGuides.

The survey is based on a detailed observation and collection of sources designated as Reference Resources in LibGuides, titles found were compiled and organized.

The results are substantial; they offered a body of specialized resources, which includes e-book collections, dictionaries, handbooks, encyclopedias and other resources that are important to electrical engineering students and researchers.

A considerable amount of resources were found; nevertheless, they represent the resources found in a randomly selected sample of LibGuides; therefore, the result is limited to the group of libraries selected.

The results of this survey are valuable to subject librarians interested in comparing resources with a pool of libraries and to discover titles that can be of interest to their collections.

The work is original, as this is the first paper publishing the results of a survey of electrical engineering guides.

The stimulus of the successful semiconductor device miniaturisation programmes coupled to recent progress in synthetic chemistry and molecular engineering has led to the emergence of a new inter‐disciplinary activity—molecular electronics—which holds long‐term promise for a new range of electronic materials and devices. From very speculative origins the field has begun to generate important applications based on photoresists, Langmuir‐Blodgett films, electroactive polymers and photochromic materials. A selection of topics ranging from molecular switches, memories, sensors, and the biological interface to prospects for a molecular computer are discussed with special emphasis on features such as stability, self‐organisation and self‐assembly which are unique to molecular systems.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

The purpose of this study is to numerically assess the misalignment-induced deformation and its implications, in the through-silicon via (TSV), silicon chip, solder micro-bump, and bonding layer.

The 3D finite element model features a TSV/micro-bump bonding structure connecting two adjacent silicon (Si) chips, with and without an underfill layer between. A case that the entire solder layer has transformed into an intermetallic layer is also considered.

The existence of an underfill layer enhances the overall resistance to shear deformation, although with a higher buildup of local stresses. High shear and tensile stresses can develop in the intermetallic and nearby regions of copper and Si if the solder alloy is replaced by an intermetallic layer. The carrier mobility change in Si may be extensively affected by the mechanical action, even in regions far away from the TSV.

This work parametrically explores the trend of stress and deformation fields due to mechanical shear and its influences on the electrical performance of devices. Potential for damage initiation in the TSV/micro-bump is also examined.