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The purpose of this paper is to identify and expand upon the understanding of the reliability of high density interconnect (HDI) technologies containing multi‐level microvia interconnections with 2, 3 or 4 stacked and staggered configured structures.

Microvia testing was performed with interconnect stress testing (IST) using a modified methodology documented in the IPC test methods manual TM650, Method 2.6.26, titled DC current induced thermal cycle test. The IST coupon designs utilize mathematical modeling, in combination with prior experience in the fields of printed wiring board (PWB) processing, chemistry, materials and statistics, to improve the sensitivity of testing.

Single and 2 stack microvias are generally the most robust type of copper interconnection used in HDI applications, 3 stack and 4 stack require greater discipline to assure product reliability. Ranking the inherent reliability of 3 stack and 4 stack structures to other interconnects like plated through holes, blind, or buried vias, may need to be reconsidered in future reliability test programs.

This work was focused on the reliability of bare board and does not address failure modes associated with the additional stresses applied to the microvia structures created by the devices and their associated solder joints formed during surface mount assembly and rework operations.

This paper was written to improve the understanding of various aspects of design and their influence on reliability for stacked and staggered microvia structures. The design function must understand the physical construction as a critical influence on microvia reliability that should be taken into consideration in parallel with the electrical requirements.

There are many advantages of microvia: it requires a much smaller pad, which saves the board size and weight; with microvia, more chips can be placed in less space or a smaller PCB, which results in a low cost; and with microvia, electrical performance improves due to a shorter pathway. Basically, there are five major processes for microvia formation: NC drilling; laser via fabrication including CO₂ laser, YAG laser, and excimer; photo‐defined vias, wet or dry; etch via fabrications including chemical (wet) etching and plasma (dry) etching; and conductive ink formed vias, wet or dry. This paper will discuss the materials and processes of these five major microvia formation methods. At the end, eight key manufacturers from Japan will be briefly illustrated for their research status and current capability of producing smallest microvia.

The purpose of this paper is to demonstrate laser microvia drilling of polyimide thin films from multiple sources before metallic sputtering. This process flow reduces Flexible Printed Circuit Board (FPCB) material, chemical and operational costs by 90 per cent in the construction of flexible circuits.

The UV laser percussion drilling of microvias in 25 μm thick polyimide films with low coefficients of thermal expansion (CTE) and elastic modulii was investigated. Results were obtained using Scanning Electron Microscopy and Surface Profilometry. Polyimide films tested included: Dupont™ Kapton^® EN; Kolon^® GP and LV; Apical^® NPI; and Taimide™ TA‐T.

There was no direct relationship between the top and bottom diameters and ablation depth rates between the polyimide films tested using the same test conditions. There was a direct relationship with exit diameters and etch rates at different laser pulse frequency rates and fluence levels. Laser pulse rates at 30 kHz produced 20 per cent larger exit diameters than at 70 kHz, however at 70 kHz the first pulse etched 16.5 per cent more material. High fluence levels etched more material but with a lower etch efficiency rate. Other microvia quality concerns such as surface swelling, membrane residues on the bottom side and surface debris inside the microvias were observed. Nanoscale powder‐like surface debris was observed on all samples in all test conditions.

This is the first comparison of material specifications and costs for films from multiple polyimide manufactures and laser microvia drilling. The paper also is the first to demonstrate results using a JDSU™ Lightwave Q302^® laser rail. The results provide the first insights into potential microvia membrane issues and debris characteristics.

Copper electrodeposition acts as a crucial step in the manufacture of high-density interconnect board. The stability of plating solution and the uniformity of copper electrodeposit are the hotspot and difficulty for the research of electrodeposition. Because a large number of factors are included in electrodeposition, experimentally determining all parameters and electrodeposition conditions becomes unmanageable. Therefore, a multiphysics coupling technology was introduced to investigate microvia filling process, and the mechanism of copper electrodeposition was analyzed. The results provide a strong theoretical basis and technical guidance for the actual electroplating experiments. The purpose of this paper is to provide an excellent tool for quickly and cheaply studying the process behavior of copper electrodeposition without actually needing to execute time-consuming and costly experiments.

The interactions among additives used in acidic copper plating solution for microvia filling and the effect on the copper deposition potential were characterized through galvanostatic measurement (GM). The adsorption behavior and surface coverage of additives with various concentrations under different rotating speeds of working electrode were investigated using cyclic voltammetry (CV) measurements. Further, a microvia filling model was constructed using multiphysics coupling technology based on the finite element method.

GM tests showed that accelerator, inhibitor and leveler affected the potential of copper electrodeposition, and bis(3-sulfopropyl) disulfide (SPS), ethylene oxide-propylene oxide (EO/PO) co-polymer, and self-made leveler were the effective additives in acidic copper plating solution. CV tests showed that EO/PO–Cu⁺-Cl⁻ complex was adsorbed on the electrode surface by intermolecular forces, thus inhibiting copper electrodeposition. Numerical simulation indicated that the process of microvia filling included initial growth period, the outbreak period and the stable growth period, and modeling result was compared with the measured data, and a good agreement was observed.

The research is still in progress with the development of high-performance computers.

A multiphysics coupling platform is an excellent tool for quickly and cheaply studying the electrodeposited process behaviors under a variety of operating conditions.

The numerical simulation method has laid the foundation for mechanism of copper electrodeposition.

By using multiphysics coupling technology, the authors built a bridge between theoretical and experimental study for microvia filling. This method can help explain the mechanism of copper electrodeposition.

CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.

Tombstoning and voiding have been plaguing the surface mount assembly industry for decades. The recent global move toward lead‐free soldering and the extensive adoption of microvia technology further aggravate the problems. The present study investigates the impact of SnAgCu (SAC) alloy composition on these important issues.

In this study, tombstoning and voiding at microvias are studied for a series of SAC lead‐free solders, with an attempt to identify a possible “composition window” for controlling these problems. Properties which may be related to these problems, such as alloy surface tension, alloy melting pattern, and solder wetting behaviour, were investigated in order to assess the critical characteristics required to control these problems.

The results indicate that the tombstoning of SAC alloys is greatly influenced by the solder composition. Both the wetting force and the wetting time at a temperature well above the melting point have no correlation with the tombstoning frequencies. Because the tombstoning is caused by imbalanced wetting forces, the results suggest that the tombstoning may be controlled by the wetting at the onset of the paste melting stage. A maximum tombstoning incidence was observed for the 95.5Sn3.5Ag1Cu alloy. The tombstoning rate decreased with increasing deviation in Ag content from this composition. A differential scanning calorimetry (DSC) study indicated that this was mainly due to the increasing presence of the pasty phase in the solders, which result in a slower wetting speed at the onset of solder paste melting stage. Surface tension plays a minor role, with lower surface tension correlating with a higher tombstoning rate. The voiding rate at the microvias was studied by employing simulated microvias. The voiding level was lowest for the 95.5Sn3.8Ag0.7Cu and 95.5Sn3.5Ag1Cu alloys, and increases with a further decrease in the Ag content. The results indicate that voiding at microvias is governed by the via filling and the exclusion of fluxes. The voiding rate decreased with decreasing surface tension and increasing wetting force, which in turn is dictated by the solder wetting or spreading. Both low surface tension and high solder wetting prevents the flux from being entrapped within a microvia. A fast wetting speed may also facilitate reducing voiding. However, this factor is considered not as important as the final solder coverage area.

In general, compositions which deviate from the ternary eutectic SAC in Ag content, particularly with a Ag content lower than 3.5Ag, exhibit a greater solid fraction at the onset of melting, resulting in a lower tombstoning rate, presumably due to a slower wetting speed. The SAC compositions with an Ag content lower than 3.5 per cent, such as 2.5Ag, resulted in a lower tombstoning rate with minimal risk of forming Ag₃Sn intermetallic platelets. On the other hand, ternary eutectic SAC exhibits a lower surface tension resulting in an easier solder spread or solder wetting, and consequently exhibit a higher tombstoning frequency and a lower incidence of voiding.

Provides a solution to the tombstoning problem in lead‐free soldering.

The present study provided a solution to the tombstoning problem encountered in lead free soldering by controlling the SAC solder alloy compositions.

As high density interconnect (HDI) technologies become accepted in the printed circuit board (PCB) industry, build‐up multilayer (BUM) technologies utilizing laser ablated microvias have grown in popularity. This paper will look at the thermal reliability of the plated blind microvias and through vias using standard thermal shock procedures and interconnect stress testing (IST) methodology. Laser ablated microvias manufactured utilizing unreinforced materials and standard FR‐4 materials will be evaluated, along with colloidal graphite direct metallization and two electroless copper processes. The thermal reliability of these different materials and processes will be determined. This paper is intended to increase BUM usage by increasing the fabricator’s understanding of the processes needed to build metallized microvias and address questions on interconnect reliability by thermal testing.

The demand for higher operating speeds and increasing densification in electronic packages is driving designers to reduce feature sizes in order to accommodate increases in I/O counts. Consequently, printed circuit board manufacturers are turning to new manufacturing techniques and new materials in order to meet these demands from their customers. Sequential build‐up is one such technique and a plethora of new materials is available to support these innovative routes to high‐density interconnect circuitry. The basic concept involves the addition of extra layers of dielectric and copper on to a multi‐layered board. The additional circuitry is then connected to the underlying board using suitably formed microvias. Focuses on the metallization of microvias using a straight‐through horizontal metallization process. Particular emphasis is placed on the importance of equipment design, the chemistry of the solutions used and optimization of fluid exchange to ensure good coverage of these small features.

Microvias or high density interconnects (HDI) printed circuits are now being designed in ever increasing quantities. HDI brings some interesting new solutions to age‐old signal integrity (SI) concerns, and concerns that will grow as rise‐times continue to drop.This article focuses on five major areas of SI concerns—(1) noise: (a) noise‐reflections, (b) noise‐crosstalk, (c) noise‐simultaneous switching; (2) electro‐magnetic interference (EMI); (3) interconnect delays.In each case, HDI offers improvements and alternatives—but it is not a panacea. A couple of “cautions” are listed that can be a major stumbling block to HDI implementation, fortunately, they are not SI based. Important to SI is the materials used in HDI. Although not the focus of this article, the materials selected, as well as the dimensional stack‐up and PCB design rules, will influence SI and electrical performance (impedance, crosstalk and signal conditioning). Miniaturization provided by HDI will be a major contributor to SI performance.Finally, the SI example is also a case study in cost reduction. The “before” and “after” conditions are reviewed to emphasize the cost reduction and “time‐to‐market” advantages of HDI technology.

In the past three years, microvia drilling using laser technology has become the dominant method of producing blind vias smaller than 150μm. The ablation characteristics of the materials used in the manufacture of PWBs can be divided into three categories: organics, glass, and metals. Organics are composed of resins and epoxies commercially available from a variety of vendors. Two types of resins that are typically used for microvia formation in the telecommunication applications are resin coated copper foil^® (RCC or RCF) for subtractive PCB process, and thermal‐curing resin (TCR) for additive PCB process respectively. This paper details the basics of UV YAG laser capabilities, alignment techniques, plating tests, reliability tests, manufacturable microvia design rules, and production experiences.