Analysis of misalignment-induced deformation in three-dimensional semiconductor chip stacks

Abstract

Purpose

The purpose of this study is to numerically assess the misalignment-induced deformation and its implications, in the through-silicon via (TSV), silicon chip, solder micro-bump, and bonding layer.

Design/methodology/approach

The 3D finite element model features a TSV/micro-bump bonding structure connecting two adjacent silicon (Si) chips, with and without an underfill layer between. A case that the entire solder layer has transformed into an intermetallic layer is also considered.

Findings

The existence of an underfill layer enhances the overall resistance to shear deformation, although with a higher buildup of local stresses. High shear and tensile stresses can develop in the intermetallic and nearby regions of copper and Si if the solder alloy is replaced by an intermetallic layer. The carrier mobility change in Si may be extensively affected by the mechanical action, even in regions far away from the TSV.

Originality/value

This work parametrically explores the trend of stress and deformation fields due to mechanical shear and its influences on the electrical performance of devices. Potential for damage initiation in the TSV/micro-bump is also examined.

Citation

W. Johnson, R. and Shen, Y.-L. (2014), "Analysis of misalignment-induced deformation in three-dimensional semiconductor chip stacks", Microelectronics International, Vol. 31 No. 2, pp. 61-70. https://doi.org/10.1108/MI-12-2013-0085