Search results

The purpose of this study is to numerically assess the misalignment-induced deformation and its implications, in the through-silicon via (TSV), silicon chip, solder micro-bump, and bonding layer.

The 3D finite element model features a TSV/micro-bump bonding structure connecting two adjacent silicon (Si) chips, with and without an underfill layer between. A case that the entire solder layer has transformed into an intermetallic layer is also considered.

The existence of an underfill layer enhances the overall resistance to shear deformation, although with a higher buildup of local stresses. High shear and tensile stresses can develop in the intermetallic and nearby regions of copper and Si if the solder alloy is replaced by an intermetallic layer. The carrier mobility change in Si may be extensively affected by the mechanical action, even in regions far away from the TSV.

This work parametrically explores the trend of stress and deformation fields due to mechanical shear and its influences on the electrical performance of devices. Potential for damage initiation in the TSV/micro-bump is also examined.

Cu/Cu diffusion bonding is characterised by high electrical and thermal conductivity, as well as the mechanical strength of the interconnects. But despite a number of advantages, Cu oxidises readily upon exposure to air. To break through the adsorbed oxide-layer high temperature and pressure, long bonding time and inert gas atmosphere are required during the bonding process. This paper aims to present the implementation of an organic self-assembled monolayer (SAM) as a temporary protective coating that inhibits Cu oxidation.

Information concerning elemental composition of the Cu surface has been yielded by X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared (FTIR) spectroscopy. Two types of substrates (electroplated and sputtered Cu) are prepared for thermocompression bonding in two different ways. In the first case, Cu is cleaned with dilute sulphuric acid to remove native copper oxide. In the second case, passivation with SAM followed the cleaning step with dilute sulphuric acid. Shear strength, fracture surface, microstructure of the received Cu/Cu interconnects are investigated after the bonding procedure.

The XPS method revealed that SAM can retard Cu from oxidation on air for at least 12 h. SAM passivation on the substrates with sputtered Cu appears to have better quality than on the electroplated ones. This derives from the results of the shear strength tests and scanning electron microscopy (SEM) imaging of Cu/Cu interconnects cross sections. SAM passivation improved the bonding quality of the interconnects with sputtered Cu in comparison to the cleaned samples without passivation.

The Cu/Cu bonding procedure was optimised by a novel preparation method using SAMs which enables storage and bonding of Si-dies with Cu microbumps at air conditions while remaining a good-quality interconnect. The passivation revealed to be advantageous for the smooth surfaces. SEM and shear strength tests showed improved bonding quality for the passivated bottom dies with sputtered Cu in comparison to the samples without SAM.

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs).

This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package.

This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package.

Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed.

The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board.

In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model.

The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

Material formulation, structuring and modification are key to increasing the unit volume complexity and density of next generation electronic packaging products. Laser processing is finding an increasing number of applications in the fabrication of these advanced microelectronic devices. The purpose of this paper is to discuss the development of new laser‐processing capabilities involving the synthesis and optimization of materials for tunable device applications.

The paper focuses on the application of laser processing to two specific material areas, namely thin films and nanocomposite films. The examples include BaTiO₃‐based thin films and BaTiO₃ polymer‐based nanocomposites.

A variety of new regular and random 3D surface patterns are highlighted. A frequency‐tripled Nd:YAG laser operating at a wavelength of 355 nm is used for the micromachining study. The micromachining is used to make various patterned surface morphologies. Depending on the laser fluence used, one can form a “wavy,” random 3D structure, or an array of regular 3D patterns. Furthermore, the laser was used to generate free‐standing nano and micro particles from thin film surfaces. In the case of BaTiO₃ polymer‐based nanocomposites, micromachining is used to generate arrays of variable‐thickness capacitors. The resultant thickness of the capacitors depends on the number of laser pulses applied. Micromachining is also used to make long, deep, multiple channels in capacitance layers. When these channels are filled with metal, the spacings between two metallized channels acted as individual vertical capacitors, and parallel connection eventually produce vertical multilayer capacitors. For a given volume of capacitor material, theoretical capacitance calculations are made for variable channel widths and spacings. For comparison, calculations are also made for a “normal” capacitor, that is, a horizontal capacitor having a single pair of electrodes.

This technique can be used to prepare capacitors of various thicknesses from the same capacitance layer, and ultimately can produce variable capacitance density, or a library of capacitors. The process is also capable of making vertical 3D multilayer embedded capacitors from a single capacitance layer. The capacitance benefit of the vertical multilayer capacitors is more pronounced for thicker capacitance layers. The application of a laser processing approach can greatly enhance the utility and optimization of new materials and the devices formed from them.

Laser micromaching technology is developed to fabricate several new structures. It is possible to synthesize nano and micro particles from thin film surfaces. Laser micromachining can produce a variety of random, as well as regular, 3D patterns. As the demand grows for complex multifunctional embedded components for advanced organic packaging, laser micromachining will continue to provide unique opportunities.

The purpose of this paper is to explore progress in electronic circuit miniaturisation, and study the new medical sensor devices emerging.

Circuit packaging advances in the mobile phone sector are examined. The products and expertise of a leading producer of non‐contact sensors and medical implants are described, followed by a series of medical applications of 3D circuitry.

Mobile phone enhancements are driving innovations in electronics that are transferable to other industries. Wafer‐thinning and 3D interconnection techniques shrink complex circuitry, enabling the construction of sensitive intelligent wireless sensors. Biologically inert packaging enables such devices to be implanted in the human body to improve sight and hearing, and monitor bone‐healing after surgery.

The paper shows how electronic packaging innovations are spinning out into non‐contact sensors and medical implants and will be of interest to engineers in these fields, and of general interest to a wider readership.

The paper aims to deal with a tuning method to reduce warpage of microelectronic substrates.

There are three major processes involved in this method: calculating effective thermomechanical properties of substrates with simple regular electric artworks using 3D finite element (FE) analyses; fitting simplified expressions to the results from the FE analyses; and developing 2D FE models of substrates with arbitrarily complicated artwork using the simplified expressions. These three processes were used to estimate the warpage. An optimization procedure through iterative searches was used to obtain optimized trace widths and/or spacing in order to reduce the warpage.

Using a printed circuit board design to prove our concept, it was found that the warpage could be significantly reduced by modifying trace widths and/or spacing of the printed circuit board.

The paper focuses on a tuning method to reduce warpage of microelectronic substrates.

To provide an insight and view of the expected directions for microelectronic packaging, at chip level, that ties in current developments to the needs envisaged by emerging technology roadmaps.

The requirements for packaging semiconductor devices have become a new technology driver for the electronics “Final Manufacturing” industry. In line with forecasts and roadmaps, the expected multitude of options are being developed in order to meet the demand of an industry which requires ever more complex devices which exhibit both higher reliability and lower cost.

As application potentials develop, so package cost becomes the driver. In turn, low cost package solutions are becoming the drivers for new technologies such as “last‐mile” fibre optic Telecom systems, 3G phones, bluetooth and sensors. MEMS devices are a key example of how applications are pushing the technologies to create cost effective packaging.

The emerging packaging technologies, currently BGA's and chip size packaging's (CSP), continue to develop to meet the needs of electronic devices, driven by the “smaller, faster, cheaper” paradigm. However the final manufacturing and testing aspects of such needs are often overlooked and as such the test industry faces a number of severe challenges in terms of handling these new package technologies.

By looking at the market trends and how these new technologies are developing, especially with respect to emerging developments in CSP, flip chip and wafer level packaging, solutions for many of the challenges posed can be determined.

This paper provides a market analysis of the trends and directions of the chip packaging industry. It has taken data from a wide number of sources of market information and compared the expectations of each to actual emerging applications. The resulting information is expected to become a benchmark for this aspect of the semiconductor manufacturing industry.

ISHM invites papers for the above Conference, to be held on 29–31 May 1991 in Rotterdam, The Netherlands. Papers should cover areas such as: design, manufacturing, packaging and interconnection, materials and processing, applications, reliability, components, new technologies, marketing and economics, optoelectronics. Summaries should be in English, length 200–300 words. The deadline for receipt of summaries is 30 September 1990. (For full details, see announcement on pp. 54–55.)

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

The increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder interconnection. As the interconnection technology for flip chip package is getting finer and smaller, it is extremely difficult to obtain the accurate values of thermal stresses by direct experimental measurements. Different types of solder bumps used for interconnection would also influence the thermal distribution within the package. Because the solder balls are too small for direct measurement of their stresses, finite element method (FEM) was used for obtaining the stresses instead.

This paper will discuss the results of the thermal stress distribution using numerical method via ABAQUS software. The variation of the thermal stress distribution with the temperature gradient model was evaluated to study the effects of the different material thermal conductivity of solder bumps used. A detailed 2D finite element model was constructed to perform 2D plain strain elastoplastic analysis to predict areas of high stress.

It is found that thermal distribution of solder bumps starts to propagate from the top region to the bottom region of the solder balls. Other than that, thermal stress effect increases in parallel with the increasing of the temperature. The simulation results shows that leaded solder balls, SnPb have higher maximum thermal stress level compared to lead‐free SAC solder balls.

The paper describes combination of stress with thermal loading correlation on a flip chip model. The work also shows how the different thermal conductivity on solder balls influences the thermal induced stress on the flip chip package.