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Article

Mei-Ling Wu and Jia-Shen Lan

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the…

Abstract

Purpose

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs).

Design/methodology/approach

This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package.

Findings

This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package.

Research limitations/implications

Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed.

Practical implications

The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board.

Social implications

In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model.

Originality/value

The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

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Article

John H. Lau

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is…

Abstract

Purpose

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

Design/methodology/approach

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

Findings

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

Originality/value

The paper's findings will be very useful to the electronic industry.

Details

Microelectronics International, vol. 28 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

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Article

Joseph Fjelstad

The purpose of this paper is to provide a historical perspective and framework for appreciating the evolution of 3D interconnection technologies from past to present.

Abstract

Purpose

The purpose of this paper is to provide a historical perspective and framework for appreciating the evolution of 3D interconnection technologies from past to present.

Design/methodology/approach

A literature and patent search was performed to find the origins of 3D interconnections to find and credit work that was performed in the early electronics industry which presaged the development of the current generation 3D solutions.

Findings

The origins of 3D interconnections have roots that date to the beginnings of electronic interconnections if the earlier solutions are viewed in proper perspective. For example, early telegraphy and telephony interconnections strung from pole to pole across large expanses of terrain were clearly 3D interconnections on a very macro scale but those solutions scaled down are not that dissimilar to what is being done today in some advanced interconnection technologies.

Research limitations/implications

The pioneers of the electronics industry broke a trail which has been widened, paved and branched by all who have followed them. Granted that the branches have led to new high‐worth discoveries but acknowledging the past and taking instruction from it is important, even necessary, to assure that future developments do not continually “reinvent the wheel”.

Originality/value

The paper traces, in brief fashion, the history of 3D interconnections providing examples of solutions which predate some of the current generation solutions which appear, in some cases, quite similar to those developed or proposed nearly half century ago. Knowing the past is vital to understanding and shaping the future.

Abstract

Details

Microelectronics International, vol. 18 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

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Article

Ming-Yue Xiong, Liang Zhang, Peng He and Wei-Min Long

The transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More…

Abstract

Purpose

The transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More than Moore. The main problems in the development of 3-D IC are Joule heating and stress. The stresses and strains generated in 3-D ICs will affect the performance of electronic products, leading to various reliability issues. The intermetallic compound (IMC) joint materials and structures are the main factors affecting 3-D IC stress. The purpose of this paper is to optimize the design of the 3-D IC.

Design/methodology/approach

To optimize the design of 3-D IC, the numerical model of 3-D IC was established. The Taguchi experiment was designed to simulate the influence of IMC joint material, solder joint array and package size on 3-D IC stress.

Findings

The simulation results show that the solder joint array and IMC joint materials have great influence on the equivalent stress. Compared with the original design, the von Mises stress of the optimal design was reduced by 69.96 per cent, the signal-to-noise ratio (S/N) was increased by 10.46 dB and the fatigue life of the Sn-3.9Ag-0.6Cu solder joint was increased from 415 to 533 cycles, indicating that the reliability of the 3-D IC has been significantly improved.

Originality/value

It is necessary to study the material properties of the bonded structure since 3-D IC is a new packaging structure. Currently, there is no relevant research on the optimization design of solder joint array in 3-D IC. Therefore, the IMC joint material, the solder joint array, the chip thickness and the substrate thickness are selected as the control factors to analyze the influence of various factors on the 3-D IC stress and design. The orthogonal experiment is used to optimize the structure of the 3-D IC.

Details

Soldering & Surface Mount Technology, vol. 32 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

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Article

Liang Zhang, Zhi-quan Liu, Fan Yang and Su-juan Zhong

This paper aims to investigate Cu/SnAgCu/Cu transient liquid phase (TLP) bonding with different thicknesses for three-dimensional (3D) integrated circuit (IC).

Abstract

Purpose

This paper aims to investigate Cu/SnAgCu/Cu transient liquid phase (TLP) bonding with different thicknesses for three-dimensional (3D) integrated circuit (IC).

Design/methodology/approach

This paper includes experiments and finite element simulation.

Findings

The growth rate of the intermetallic compound layer during TLP soldering was calculated to be 0.6 μm/s, and the small scallop-type morphology Cu6Sn5 grains can be observed. With the decrease in thickness in solder joint, the thickness of intermetallic compounds represents the same size and morphology, but the size of eutectic particles (Ag3Sn, Cu6Sn5) in the matrix microstructure decrease obviously. It is found that with the increase in thickness, the tensile strength drops obviously. Based on finite element simulation, the smaller value of von Mises demonstrated that the more reliability of lead-free solder joints in 3D IC.

Originality/value

The Cu/SnAgCu/CuTLPbondingwithdifferentthicknessesfor3D IC was investigated.

Details

Soldering & Surface Mount Technology, vol. 29 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Abstract

Details

Soldering & Surface Mount Technology, vol. 15 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Abstract

Details

Circuit World, vol. 29 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Abstract

Details

Microelectronics International, vol. 20 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

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Article

M.H.H. Ishak, Farzad Ismail, Mohd Sharizal Abdul Aziz and M.Z. Abdullah

The purpose of this study is to investigate the effect of the adhesive force and density ratio using lattice Boltzmann method (LBM) during underfill process.

Abstract

Purpose

The purpose of this study is to investigate the effect of the adhesive force and density ratio using lattice Boltzmann method (LBM) during underfill process.

Design/methodology/approach

To deal with complex flow in underfill process, a framework is proposed to improve the lattice Boltzmann equation. The fluid flows with different density ratio and bump arrangement in underfill are simulated by the incorporated Carnahan–Starling (CS) equation of state (EOS). The numerical study conducted by finite volume method (FVM) and experimental results are also presented in each case at the different filling percentage for verification and validation purpose.

Findings

The numerical result is compared well with those acquired experimentally. Small discrepancy is detected in their flow profile. It was found that the adhesive force between fluid and solid was affected by the density ratio of the fluids and solder bump configuration. LBM has shown better adhesive force effect phenomenon on underfill process compared to FVM. LBM also demonstrated as a better tool to study the fluid flow in the underfill process.

Practical implications

This study provides a basis and insights into the impact of adhesive force and density ratio to the underfill process that will be advancing the future design of flip chip package. This study also provides superior guidelines, and the knowledge of how adhesive force is affected by flip chip package structure.

Originality/value

This study proposes the method to predict the adhesive force and density ratio effect for underfill flow in flip chip package. In addition, the proposed method has a good performance in representing the adhesive force during the underfill simulation for its natural physical basic. This study develops understanding of flow problems to attain high reliability for electronic assemblies.

Details

Microelectronics International, vol. 37 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

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