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The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack.

This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point.

The results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level.

There is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.

A W-band antennas-in-packages (AIP) module with a hybrid stacked glass-compound wafer level fan-out process was presented. Heterogeneous radio frequency (RF) chips were integrated into one single module with a microscale fan-out process. This paper aims to find a new strategy for 5G communication with 3D integration of multi-function chips.

The AIP module was composed of two stacked layers: the antenna layer and RF layer. After architecture design and performance simulation, the module was fabricated, The 8 × 8 antenna array was lithography patterned on the 12 inch glass wafer to reduce the parasitic parameters effect, and the signal feeding interface was fabricated on the backside of the glass substrate.

AIP module demonstrates a size of 180 mm × 180mm × 1mm, and its function covers the complete RF front-end chain from the antenna to signal to process and can be applied in 5 G communication and automotive components.

With three RF multi-function chips and two through silicon via (TSV) chips were embedded in the 12 inch compound wafer through the fan-out packaging process; two layers were interconnected with TSV and re-distributed layers.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss.

An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples.

The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth.

The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions.

This study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.

The copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.

It can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.

It is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).

In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.

It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.

In this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

Modern semiconductor technologies have advanced to the level of sophistication where the benefits of the high functional and power density, high speed, low defect rate and low wafer processing cost can seldom be fully utilised at the final equipment or even at the single packaged semiconductor component level due to the limitations of wire bonds and lead frame fan‐outs. This paper suggests a new assembly method where low‐cost contact bumps are deposited on semiconductor wafers and then the dice are reflow soldered or gang bonded to the substrate. The bumps are electroless nickel deposited and coated with a protective layer of gold. As the nickel bumps are non‐collapsible, they are better suited to Extra High Density Interconnections (EHDI) than the more usual solder bumps. The amount of solder must be accurately dispensed either on the die bumps or on the substrate bonding pads using various methods. Essential to the high volume assembly is fast pick‐and‐place operation and simultaneous soldering of all components in a reflow furnace. In certain applications bonding of the bumped device (one die at a time) can be done using reflow or thermocompression gang bonding by applying a heated thermode to the backside of the die. In this case, the bonding energy will be transferred through the die to the bumps. Tentative solder joint strength and reliability aspects are discussed. Further process and design improvements are suggested.