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This paper aims to study the various developments taking place in the field of gas sensors made from polyaniline (PANI) nanocomposites, which leads to the development of high-performance electrical and gas sensing materials operating at room temperature.

PANI/ferrite nanocomposites exhibit good electrical properties with lower dielectric losses. There are numerous reports on PANI and ferrite nanomaterial-based gas sensors which have good sensing response, feasible to operate at room temperature, requires less power and cost-effective.

This paper provides an overview of electrical and gas sensing properties of PANI/ferrite nanocomposites having improved selectivity, long-term stability and other sensing performance of sensors at room temperature.

The main purpose of this review paper is to focus on PANI/ferrite nanocomposite-based gas sensors operating at room temperature.

This review aims to give an overview about zinc oxide (ZnO) based gas sensors and the role of doping in enhancing the gas sensing properties. Gas sensors based on ZnO thin film are preferred for sensing applications because of their modifiable surface morphology, very large surface-to-volume ratio and superior stability due to better crystallinity. The gas detection mechanism involves surface reaction, in which the adsorption of gas molecules on the ZnO thin film affects its conductivity and reduces its electrical properties. One way to enhance the gas sensing properties is by doping ZnO with other elements. A few of the common and previously used dopants include tin (Sn), nickel (Ni) and gallium (Ga).

In this brief review, previous works on doped-ZnO formaldehyde sensing devices are presented and discussed.

Most devices provided good sensing performance with low detection limits. The reported operating temperatures were within the range of 200̊C –400̊C. The performance of the gas sensors can be improved by modifying their nanostructures and/or adding dopants.

As of yet, a specific review on formaldehyde gas sensors based on ZnO metal semiconductors has not been done.

The purpose of this study is to present reports on fabrication of silicon (Si) nanowires (NWs). The study consists of microwire formation on silicon-on-insulator (SOI) that was fabricated using a top-down approach which involved conventional photolithography coupled with shallow anisotropic etching.

A 5-inch p-type silicon-on-insulator (SOI) coated with 250nm layer and Photoresist (PR) with thickness of 400nm is coated in order to make pattern transfer via binary mask, after the exposure and development, a resist pattern between 3 μm-5 μm were obtained, Oxygen plasma spreen was used to reduce the size of the PR to 800 μm, after this, the wafer with 800 μm was loaded into SAMCO inductively coupled plasma (ICP)-RIE and got silicoon microwire was obtained. Next, the sample was put into an oxidation furnace for 15, 30, 45 and 60 minutes and the sample was removed and dipped into a buffered oxide etch solution for five minutes to remove all the SiO₂ ashes.

The morphological characterization was conducted using scanning electron microscopy and atomic force microscopy. At terminal two, gold electrodes which were designated as source and drain were fabricated on top of individual NWs using conventional lithography electrical and chemical response. Once the trimming process has been completed, the device's current–voltage (I-V) characteristic was measured by using a Keithley 4200 semiconductor parameter analyser. Devices with different width of wires approximately 20, 40, 60 and 80 nm were characterized. The wire current variation as a function of the pH variation in voltage was investigated: pH monitoring for variations of pH values between 5 and 9.

This paper provides useful information on novel and yet simple cost-effective fabrication of SiNW; as such, it should be of interest to a broad readership, especially those interested in micro/nanofabrication.

The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.

A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.

Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.

Comparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

This paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V.

The analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE.

This paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device.

The proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

The purpose of this paper is to design an out-of-plane micro electro-thermal-compliant actuator based logic gates which work analogously to complementary metal oxide semiconductor (CMOS) based logic gates. The proposed logic gates used a single-bit mechanical micro ETC actuator per logic instead of using 6-14 individual transistors as in CMOS.

A complete analytical modelling is performed on a single ETC vertical actuator, and a relation between the applied voltage and the out-of-plane deflection is derived. Its coupled electro-thermo-mechanical analysis is carried out using micro electro mechanical system (MEMS) CAD tool CoventorWare to illustrate its performance.

This paper reports analytical and numerical simulation of basic MEMS ETC actuator-based logic gates. The proposed logic gate operates on 5 V, which suits well with conventional CMOS logic, which in turn reduces the power consumption of the device.

The proposed logic gates uses a single-bit MEMS ETC actuator per logic instead of using more transistors as in CMOS. The unique feature of this proposed logic gates is that the basic mechanical ETC actuator is customized in its structure to function as specific logic gates depending upon the given inputs.

The purpose of this paper is to examine the growth and characterization of the two different compound semiconductors, namely, n-zinc oxide (ZnO) and p-gallium antimonide (GaSb). In this paper, fabrication and characterization of n-ZnO/p-GaSb heterojunction diode is analyzed.

Thermo vertical direction solidification (TVDS) method was used to synthesize undoped GaSb ingot from high purity Ga (5N) and Sb (4N) host materials. Thermal evaporation technique is used to prepare a film of GaSb on glass substrate from the pre-synthesized bulk material by TVDS method. Undoped ZnO film was grown on GaSb film by sol–gel method by using chemical wet and dry (CWD) technique to fabricate n-ZnO/p-GaSb heterojunction diode.

The formation of crystalline structure and surface morphological analysis of both the GaSb bulk and film have been carried out by x-ray diffraction (XRD) analysis and scanning electron microscopy analysis. From the XRD studies, the structural characterization and phase identification of ZnO/GaSb interface. The current–voltage characteristic of the n-ZnO/p-GaSb heterostructure is found to be rectifying in nature.

GaSb film growth on any substrate by thermal evaporation method taking a small piece of the sample from the pre-synthesized GaSb bulk ingot has not been reported yet. Semiconductor device with heterojunction diode by using two different semiconductors such as ZnO/GaSb was used by this group for the first time.

Amalgams, which are mechanically alloyed mixes of a liquid metal with a powder, offer advantages in situations where large devices are to be bonded to materials with significant coefficient of expansion differences or where extremely temperature‐sensitive devices are to be bonded. This is because these materials will set or harden at or near room temperature to yield hard metallic bonds with melting points from 280°C up to ∼600°C depending upon the systems used. In this paper the results of a survey study of three binary systems of gallium with copper, nickel and silver are described. Wetting characteristics, bond strengths with and without metallisation, bulk properties including electrical and thermal properties and thermal cycle performance of joints are described. The feasibility of using these materials for bonding metallised and unmetallised surfaces of a variety of ceramics and semiconductors is clearly demonstrated.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

The purpose of this study is to improve the performance of AISI 430 stainless steel (430 SS) in increasing its oxidation resistance, suppressing coating spalling and cracking, sustaining appropriate conductivity and blocking Cr evaporation as an interconnect material for intermediate temperature solid oxide fuel cells; a protective co-contained coating is formed onto stainless steel via the surface alloying process and followed by thermal oxidation.

In this work, oxidation behavior of coated specimen is studied during isothermal and cyclic oxidation measurements. Moreover, the conductivity is also investigated by area specific resistance (ASR) measurement.

Co-contained spinel layer shows an outstanding performance in preventing oxidation and improving conductivity compared with uncoated specimens. The protective spinel coating also reduces the ASR for coated specimen (0.0576O cm²) as compared to the uncoated specimen (1.87296O cm²) after isothermal oxidation.

The probable mechanism of co-contained alloy converting into spinel and the spinel transfer electron is presented.