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The purpose of this paper is to present a selective wet‐etching method of boron doped low‐pressure chemical vapour deposition (LPCVD) polysilicon film for the realization of piezoresistors over the bulk micromachined diaphragm of (100) silicon with improved yield and uniformity.

The method introduces discretization of the LPCVD polysilicon film using prior etching for the grid thus dividing each chip on the entire wafer. The selective etching of polysilicon for realizing of piezoresistors is limited to each chip area with individual boundaries.

The method provides a uniform etching on the entire silicon wafer irrespective of its size and leads to economize the fabrication process in a batch production environment with improved yield.

The method introduces one extra process step of photolithography and subsequent etching for discretizing the polysilicon film.

The method is useful to enhance yield while defining metal lines for contact purposes on fabricated electronic structures using microelectronics. Stress developed in LPCVD polysilicon can be removed using proposed approach of discretization of polysilicon film.

The work is an outcome of regular fabrication work using conventional approaches in an R&D environment. The proposed method replaces the costly reactive ion etching techniques with stable reproducibility and ease in its implementation.

As the feature sizes of microelectronic and optoelectronic components continue to decrease, there has been increased interest in developing new techniques for etching the materials used to construct these highly integrated components. Features of the new techniques now being investigated include etching with neutral species, maskless processing, material selectivity, and reduced electrical damage.

The purpose of this paper is to synthesize porous zinc oxide (ZnO) by means of strain etching/wet chemical etching method with the use of 0.5% of nitric acid (HNO₃) etchant. The structural and surface morphological properties of the samples are accessed by using X‐ray diffraction (XRD) and scanning electron microscopy (SEM) characterization techniques.

ZnO samples used in this work were deposited on the p‐Si (111) substrates by using radio frequency (RF) sputtering technique. Wet chemical etching processes with the use of 0.5% HNO₃ etchant was applied on these samples in order to obtain porous structure. The porous ZnO samples are characterized by means of XRD and SEM to access their structural and surface morphological properties.

The XRD and SEM cross‐sectional measurements revealed that the thickness of the etched ZnO thin films is proportional to the etching time. SEM micrographs show that the surface morphology of ZnO changes over etching time. On the other hand, XRD results indicate that the crystallite sizes of the ZnO(002) decreases when the etching time increases.

The paper shows how porous ZnO thin films have been successfully synthesized by using simple wet chemical etching. SEM images reveal that this method is reliable when producing porous structure ZnO surfaces.

This paper aims to develop an ideal technique for the preparation of print circuit boards (PCBs) with ladder conductive lines on practical industrial process lines.

First, the raw materials of ladder copper-clad laminates were prepared by plating double-sided copper-clad laminates with vertical plating line. Second, etching compensation experiments were designed and conducted to set up the relationships between etching compensation and width of conductive lines on ladder line print circuit boards (LLPCBs). Third, to evaluate the process technique for the preparation of LLPCBs through etching compensation, verification experiments were designed and conducted on a practical industrial process line, and the quality of lines on LLPCBs was observed and evaluated.

Under the judgment of the quality of conductive lines on LLPCBs as well as the feasibility with a practical industrial process line, the process technique for the preparation of LLPCBs with etching compensation is a simple and reliable method which has the potential to be applied in the industry.

It is the first successful report of a new method that produces LLPCBs with etching compensation and has the potential to be applied in the industry.

The subtractive method is widely used to produce high‐density PWBs. It is generally accepted that a pattern pitch of 100 microns or less cannot be achieved by the subtractive method because of the thickness of the copper layer to be etched. We report here on experiments to investigate the relationship between the pattern pitch of a circuit formed by the subtractive method and the required thickness of the copper layer. We have also determined the allowable thickness of the copper layer, plating layer, and copper foil layer for achieving a pattern pitch of 100 microns (L/S = 50/50 microns) or less.

The purpose of this paper is to investigate the morphology of intermetallic (IMC) compounds and the mechanical properties of SAC305 solder alloy under different cooling conditions.

SAC305 solder joints were prepared under different cooling conditions/rates. The performance of three different etching methods was investigated: simple chemical etching, deep etching based on the Jackson method and selective removal of β-Sn by a standard three-electrode cell method. Phase and structural analyses were conducted by X-ray diffraction (XRD). The morphology of etched solder was examined by a field emission scanning electron microscope. The hardness evaluations of the solder joints were conducted by a Vickers microhardness tester.

The Ag₃Sn network was significantly refined by the ice-quenching process. Further, the thickness of the Cu₆Sn₅ layer decreased with an increase in the cooling rate. The finer Ag₃Sn network and the thinner Cu₆Sn₅ IMC layer were the results of the reduced solidification time. The ice-quenched solder joints showed the highest hardness values because of the refinement of the Ag₃Sn and Cu₆Sn₅ phases.

The reduction in the XRD peak intensities showed the influence of the cooling condition on the formation of the different phases. The micrographs prepared by electrochemical etching revealed better observations regarding the shape and texture of the IMC phases than those prepared by the conventional etching method. The lower grain orientation sensitivity of the electrochemical etching method (unlike chemical etching) significantly improved the micrographs and enabled accurate observation of IMC phases.

The purpose of this study is to explore the mechanism of branch pits and tunnels formation and increase the specific surface area and capacitance of anode Al foil for high voltage electrolytic capacitor by D.C. etching in acidic solution and neutral.

Al foil was first D.C. etched in HCl-H₂SO₄ mixed acidic solution to form main tunnels perpendicular to the Al surface, and then D.C. etched in neutral NaCl solution including 0.5 per cent C₆H₈O₇ and Cu(NO₃)₂ with different concentration to form branch tunnels normal to Al surface. Between two etching, Cu nuclei were electroless deposited on the interior surface of main tunnels by natural occluded corrosion cell effect to form micro Cu-Al galvanic local cells. The effects of electroless deposited Cu nuclei on cross-section etching morphologies and electrochemical behavior of Al foil was investigated with SEM, polarization curve and electrochemical impedance spectroscopy (EIS).

The results show that sub branch tunnels can form along the main tunnels owing to the formation of Cu-Al micro-batteries, in which Cu is cathode and Al is anode. With increase in Cu(NO₃)₂ concentration, more Cu nuclei can be electroless deposited and serve as the favorable sites for branch tunnel initiation along the whole length of main tunnels, leading to enhancement in specific capacitance of anode Al foil.

Cu nuclei were electroless deposited on the interior surface of main tunnels by natural occluded corrosion cell effect to form micro Cu-Al galvanic local cells, which can serve as the favorable sites for branch tunnel initiation along the main tunnels to enhance specific capacitance of anode Al foil.

The purpose of this paper is to present the influence of gate dielectric etching on obtained MISFET (metal insulator semiconductor field effect transistor) structures. Because of its properties, aluminum nitride (AlN) layers can be successfully used in a large area of applications. In addition, AIN has a wide bandgap (6.2eV) and high thermal conductivity (3.2 W/cm * K). Its melting temperature is greater than 2,000°C. The relative permittivity is about 9. All these features (especially high power, high temperature and high-frequency) make AlN a useful material in the fields of electronic, optical and acoustic applications.

To fabricate n-channel transistors, silicon technology was used. The 50-nm thick AlN films were deposited using the magnetron sputtering. After preparation of SiO₂/AlN stack as the gate dielectric, the optimization processes of dry etching in plasma environment by Taguchi method were realized. In the next step, three methods of AlN etching were selected and used to MISFET device fabrication. Atomic force microscopy and scanning electron microscopy allowed to surfacing of the state observation after etching process. The current–voltage (I–V) output and transfer characteristics of structures with modified etch technology were measured. Keithley SMU 236/237/238 measurement set was used.

In this research work, a method of AlN etching in a field effect transistor technology was developed and improved. Current−voltage characteristics of obtained MISFET structures were measured and compared. Influence of etching procedure on transistors properties was examined.

The obtained results allow improving the MISFET technology based on AlN film as a gate dielectric. The complete research work will allow using the developed technologies to implement in highly sensitive ion-sensitive field effect transistor (ISFET) structures in the future. The improvement of the etching element in the technology strongly influences the detection capabilities and operating range of the transistor.

The purpose of this paper is to introduce trench termination for high power buried‐gate static induction transistor (SIT) comprising three parts, which can inhibit the reverse leakage current substantially and paradisaical current. The simplified step‐etching process will also be discussed in detail.

For power buried‐gate SIT, the trench termination comprises three grooves, gate electrode etching, mesa‐groove etching and the separated groove, respectively. The simplified step‐etching process is proposed to optimize the traditional technical processing.

The tripartite trench termination of power SIT can inhibit the reverse leakage current, improve the gate‐source breakdown and increase the blocking voltage. The step‐etching process which is proposed for the first time, realizes the tripartite trench termination simultaneously which simplifies the traditional processes and is beneficial by protecting the surface of the die. The optimum etched depth of termination is also presented with experimentations.

The tripartite trench termination of power SIT is novel and the step‐etching process is also proposed for the first time.

To fabricate submicrometer thin membrane of silicon nitride and silicon dioxide over an anisotropically etched cavity in (100) silicon.

PECVD of silicon dioxide and Silcion nitride layers of compatible thicknesses followed by thermal annealing in nitrogen ambients at 1,000°C for 30 min, leads to stable membrane formation. Anisotropic etching of (100) silicon below the membrane through channels on the sides has been used with controlled cavity dimensions.

Lateral front side etching through channels slows down etching rate drastically. The etching mechanism has been discussed with experimental details.

Vacuum sealed cavity membranes can be realised for micro sensor applications.

The process is new and feasible for micro sensor technologies.