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Recent progress in silicon—on—insulator (SOI) technologies has made possible the fabrication of high quality ultra—thin film structures. Preliminary research has demonstrated the advantage of fully—depleted SOI MOSFET's in term of speed and improved resistance to hot carrier degradation. The specific dual‐gate configuration of SOI transistors is schematically presented in Fig. 1(a).

The purpose of this study is to present reports on fabrication of silicon (Si) nanowires (NWs). The study consists of microwire formation on silicon-on-insulator (SOI) that was fabricated using a top-down approach which involved conventional photolithography coupled with shallow anisotropic etching.

A 5-inch p-type silicon-on-insulator (SOI) coated with 250nm layer and Photoresist (PR) with thickness of 400nm is coated in order to make pattern transfer via binary mask, after the exposure and development, a resist pattern between 3 μm-5 μm were obtained, Oxygen plasma spreen was used to reduce the size of the PR to 800 μm, after this, the wafer with 800 μm was loaded into SAMCO inductively coupled plasma (ICP)-RIE and got silicoon microwire was obtained. Next, the sample was put into an oxidation furnace for 15, 30, 45 and 60 minutes and the sample was removed and dipped into a buffered oxide etch solution for five minutes to remove all the SiO₂ ashes.

The morphological characterization was conducted using scanning electron microscopy and atomic force microscopy. At terminal two, gold electrodes which were designated as source and drain were fabricated on top of individual NWs using conventional lithography electrical and chemical response. Once the trimming process has been completed, the device's current–voltage (I-V) characteristic was measured by using a Keithley 4200 semiconductor parameter analyser. Devices with different width of wires approximately 20, 40, 60 and 80 nm were characterized. The wire current variation as a function of the pH variation in voltage was investigated: pH monitoring for variations of pH values between 5 and 9.

This paper provides useful information on novel and yet simple cost-effective fabrication of SiNW; as such, it should be of interest to a broad readership, especially those interested in micro/nanofabrication.

To develop a silicon lateral Schottky rectifier with low forward voltage drop and low reverse leakage current while its breakdown voltage is significantly larger than that of a conventional Schottky rectifier.

A two‐dimensional device simulation has been used, to examine the effect lateral dual sidewall Schottky concept on the current‐voltage characteristics of a lateral Schottky rectifier on silicon‐on‐insulator. The Schottky contact consists of a low‐barrier metal and a high‐barrier metal.

Results show that, during forward bias, the low‐barrier Schottky (LBS) contact conducts resulting in a low forward voltage drop. During the reverse bias, the LBS contact is shielded by the depletion region of the high‐barrier Schottky contact resulting in a low reverse leakage current.

With this approach, silicon Schottky rectifiers with low power dissipation and improved breakdown voltage can be realized.

The proposed device has a large commercial potential as a low‐power high‐voltage switching device.

The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition.

The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation.

We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime.

The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

This paper aims to propose a method to reduce the resistance of silicon-based V-shaped electrothermal microactuator (VEM) by applying a surface sputtering process.

Four VEM’s samples have been fabricated using traditional silicon on insulator (SOI)-Micro-electro-mechanical System (MEMS) technology, three of them are coated with a thin layer of platinum on the top surface by sputtering technique with different sputtered times and the other is original. The displacements of the VEM are calculated and simulated to evaluate the advantages of sputtering method.

The measured results show that the average resistance of the sputtered structures is approximately 1.16, 1.55 and 2.4 times lower than the non-sputtering sample corresponding to the sputtering time of 1.5, 3 and 6 min. Simulation results confirmed that the maximum displacement of the sputtered VEM is almost 1.45 times larger than non-sputtering one in the range of voltage from 8 to 20 V. The experimental displacements are also measured to validate the better performance of the sputtered samples.

The experimental results demonstrated the better displacement of the VEM structure after using the platinum sputtering process. The improvement can be considered and applied for enhancing displacement as well as decreasing the driving voltage of the other electrothermal microactuators like U- or Z-shaped structures while combining with the low-cost SOI-MEMS micromachining technology.

To detail results of research into optical waveguides fabricated from silicon on insulator (SOI) for on‐chip high speed applications and from polymer for more general applications.

This paper shows the processes for wet etch fabrication of SOI single mode rib waveguides including compact crystal plane turning mirrors. Losses for the mirror facets are determined by difference measurements. Multimode polymer strip waveguides are fabricated on glass substrates by conventional photolithography using SU8 polymer and tested for attenuation.

Fabrication of compact turning mirrors for silicon waveguides requires precise alignment of masks and controlled etching of the corner facets in order to obtain correct alignment of the mirror face with the incoming and outgoing waveguides. Measurements of losses per mirror facet show typical losses of 1‐2 dB/facet. Suggestions for improvements are made. Preliminary results for polymer waveguides show the necessity for high quality lithography.

Optical interconnects for high speed communication on board and on chip are part of the ITRS Road Map for advanced interconnects. Design of optical elements to enable this, including reduction of on‐chip area by turning mirrors, is necessary for on‐chip optical technology to be successful. Compact etched mirrors described here extend previous designs and enable fabrication at any position on‐chip. New etch mask techniques for silicon waveguide fabrication are also described.

This paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.

A new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.

The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.

The proposed bit-cell is novel compared with existing bit-cells.

Structures play a very important role in developing pressure sensors with good sensitivity and linearity, as they undergo deformation to the input pressure and function as the primary sensing element of the sensor. To achieve high sensitivity, thinner diaphragms are required; however, excessively thin diaphragms may induce large deflection and instability, leading to the unfavorable performances of a sensor in terms of linearity and repeatability. Thereby, importance is given to the development of innovative structures that offer good linearity and sensitivity. This paper aims to investigate the sensitivity of a bossed diaphragm coupled fixed guided beam three-dimensional (3D) structure for pressure sensor applications.

The proposed sensor comprises of mainly two sensing elements: the first being the 3D mechanical structure made of bulk silicon consisting of boss square diaphragm along with a fixed guided beam landing on to its center, forming the primary sensing element, and the diffused piezoresistors, which form the secondary sensing element, are embedded in the tensile and compression regions of the fixed guided beam. This micro mechanical 3 D structure is packaged for applying input pressure to the bottom of boss diaphragm. The sensor without pressure load has no deflection of the diaphragm; hence, no strain is observed on the fixed guided beam and also there is no change in the output voltage. When an input pressure P is applied through the pressure port, there is a deformation in the diaphragm causing a deflection, which displaces the mass and the fixed guided beam vertically, causing strain on the fixed guided beam, with tensile strain toward the guided end and compressive strain toward the fixed end of the close magnitudes. The geometrical dimensions of the structure, such as the diaphragm, boss and fixed guided beam, are optimized for linearity and maximum strain for an applied input pressure range of 0 to 10 bar. The structure is also analyzed analytically, numerically and experimentally, and the results are compared.

The structure offers equal magnitudes of tensile and compressive stresses on the surface of the fixed guided beam. It also offers good linearity and sensitivity. The analytical, simulation and experimental studies of this sensor are introduced and the results correlate with each other. Customized process steps are followed wherein two silicon-on-insulator (SOI) wafers are fusion bonded together, with SOI-1 wafer used to realize the diaphragm along with the boss and SOI-2 wafer to realize the fixed guided beam, leading to formation of a 3D structure. The geometrical dimensions of the structure, such as the diaphragm, boss and fixed guided beam, are optimized for linearity and maximum strain for an applied input pressure range of 0 to10 bar.

This paper presents a unique and compact 3D micro-mechanical structure pressure sensor with a rigid center square diaphragm (boss diaphragm) and a fixed guided beam landing at its center, with diffused piezoresistors embedded in the tensile and compression regions of the fixed guided beam. A total of six masks were involved to realize and fabricate the 3D structure and the sensor, which is presumed to be the first of its kind in the fabrication of MEMS-based piezoresistive pressure sensor.

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.

The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.

A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.

Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

The purpose of this paper was to develop a novel capacitive micromachined ultrasonic transducer (CMUT) reception and transmission linear array for underwater imaging at 400 kHz. Compared with traditional CMUTs, the developed transducer array offers higher electromechanical coupling coefficient and higher directivity performance.

The configuration of the newly developed CMUT reception and transmission array was determined by the authors’ previous research into new element structures with patterned top electrodes and into directivity simulation analysis. Using the Si-Silicon on insulator (Si-SOI) bonding technique and the principle of acoustic impedance matching, the CMUT array was fabricated and packaged. In addition, underwater imaging system design and testing based on the packaged CMUT 1 × 16 array were completed.

The simulation results showed that the optimized CMUT array configuration was selected. Furthermore, the designed configuration of the CMUT 1 × 16 linear array was good enough to guarantee high angular resolution. The underwater experiments were conducted to demonstrate that this CMUT array can be of great benefit in imaging applications.

Based on our research, the CMUT linear array has good directivity and good impedance matching with water and can be used for obstacle avoidance, distance measurement and imaging underwater.

This research provides a basis for CMUT directivity theory and array design. CMUT array presented in this paper has good directivity and has been applied in the underwater imaging, resulting in a huge market potential in underwater detection systems.