Design and simulation of electrostatic NEMS logic gates

P. Pandiyan (Department of Electrical and Electronics Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India)
G. Uma (Department of Instrumentation and Control Engineering, National Institute of Technology, Tiruchirappalli, India)
M. Umapathy (Department of Instrumentation and Control Engineering, National Institute of Technology, Tiruchirappalli, India)

Abstract

Purpose

This paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V.

Design/methodology/approach

The analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE.

Findings

This paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device.

Originality/value

The proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

Keywords

Citation

Pandiyan, P., Uma, G. and Umapathy, M. (2018), "Design and simulation of electrostatic NEMS logic gates", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 37 No. 1, pp. 2-28. https://doi.org/10.1108/COMPEL-12-2016-0544

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Publisher

:

Emerald Publishing Limited

Copyright © 2018, Emerald Publishing Limited


1. Introduction

Recent developments in micro fabrication technology and severe requirement for enhanced complementary metal oxide semiconductor (CMOS) systems have enabled the production of many remarkable micro and nano scale devices. Nanoelectromechanical system (NEMS) switches can be substituted for CMOS transistors in terms of resulting in higher efficiency, higher isolation, near zero sub threshold leakage, extremely low sub threshold swing values (Taur and Ning, 1998; Abele et al., 2005), insensitive to temperature and ionizing radiation (Lee et al., 2005) as compared to CMOS transistors. The continuous improvement in the processing performance of electronic components has been achieved by a constant reduction of the transistor size in metal-oxide semiconductor (MOS) technology. The increased performance of integrated circuits (ICs) is also associated with increase in packing density thus reducing the cost. Apart from this, these MOS devices cannot be used under extreme temperature and radiation conditions (Streetman and Banerjee, 1999; Srour and McGarrity, 1988; Johnstone et al., 2002), thereby limiting their uses in military and space applications. The physical limitations of the current technology have motivated the researchers to look for alternative ways to process information for specific applications. The proposed NEMS logic gate is a NEMS device capable of performing Boolean logic functions, similar to conventional solid-state logic gates, yet inheriting all the features of a NEMS switch and thus expected to have diverse range of applications instead of existing switches. It also offers flexibility of making digital interface in the NEMS structure itself, thus reducing the difficulty of realizing NEMS-based system on chip (SoC) systems (Lee et al., 2005).

Dadgour et al. (2010a, 2010b) demonstrated the design of logic gates using an MOSFET like mechanical transistor, same as conventional solid state transistor. It requires two laterally actuated double electrode NEMS device to implement the logic gates such as Inverter, NOT AND (NAND), NOT OR (NOR) and exclusive – or gate (XOR) and its pull-in voltage approximately 20 V. Dadgour et al. (2010a, 2010b) also reported the simplified design of full adder based on laterally actuated NEMS-based XOR gates. Pai and Tabib-Azar (2014) implemented the logic gates such as all or nothing gate (AND), any or all gate (OR) and XOR gates using microplasma with operating voltage in between 5 and 40 V with foot size of 50 × 5 μm. Sinha et al. (2012) reported the inverter, NAND and NOR mechanical logic gates using body-biased Aluminum Nitride (AlN) piezoelectric MEMS switches with operating swing voltages of ±2 V. Parsa et al. (2013) implemented the 2 × 1 multiplexer using laterally actuated platinum-coated polysilicon NEM relays with operating gate pulse voltage of 10.75 V and beam voltage of 1 V. Rochus et al. (2013) reported the design of inverters, NAND gate and ring oscillator based on NEMS relay which works similar to CMOS-based devices. Seyedi et al. (2015) proposed content addressable memory component using NEM switches and CMOS transistors to realize the translation lookaside buffers with 16 nm technology works at 2 GHz for accessing data and instructions to complete the search operation within one clock cycle. Samaali et al. (2015) reported mathematical modeling and finite element method solution for electrostatic-based single pole double throw switch (SPDT) micro switch used in a wireless sensor. The logic gates reported in literature works in the range of 0V to 40V, involves more NEMS switches with complex structures too. The logic gates proposed in this work overcome above mentioned limitations and uses only single NEMS switch with operating voltage of 0-5V which makes it compatible with SoC.

This paper describes about the electrostatic NEMS-based logic gates such as Inverter, XOR, XNOR, NAND, OR and AND/NOR gate using laterally actuated double electrode NEMS structures which works in 5 V. The proposed logic gates are analogous to the CMOS-based logic gates. The electro-static actuation is chosen for implementing the logic gates, and it is compatible with IC technologies. The reliability of NEMS switches is studied (Peschot et al., 2015), and it is concluded that choosing the best contact material is the key to overcome the reliability challenge for NEMS switches. A thin coating of titanium oxide is used in cantilever beam (source) to improve the reliability of the proposed NEMS switches. The cyclic switching of the laterally actuated NEMS switches is more compared to vertical-actuated NEMS switches. The proposed logic gates can be used to build a non-volatile memory circuit (Yang et al., 2011), oscillators (Munoz-Gamarra et al., 2012), signal processing circuit for low frequency sensor applications (Chakraborty and Bhattacharyya, 2010) and switches for power applications(Keimel et al.,2012).

2. Device structure and operating principle

NEMS switch is designed based on the principle of electrostatic actuation of cantilever beam. Figure 1(a) shows a top view of the device structure which consists of two gate electrodes (Gate A and Gate B), source (cantilever beam) and drain (output). Gate electrodes can be controlled independently for the deflection of cantilever beam by applying the voltage. If a potential difference exists between the Gate A (or Gate B) and the cantilever, an electrostatic force is created which deflects the beam toward the Gate A (or Gate B). If the difference in voltage between Gate A (or Gate B) and cantilever beam is greater than pull-in voltage of the beam, then cantilever beam touches the drain in the direction of the Gate A (or Gate B). When the beam touches the drain, a conduction path is created between the source and drain. The voltage applied to Gate A and Gate B are called Configuration I and Configuration II, respectively.

3. Logic gate design

The cantilever beam-based logic gates such as Inverter, AND/NOR, OR, NAND, XOR and XNOR gates are realized using the laterally actuated double electrode NEMS device. The unique feature of this device is that it can perform different logic functions depending on the input signal without changing the mechanical structure.

3.1 Inverter

Inverter can be implemented using NEMS device as shown in Figure 2, and its dimensions are given in Table I. In this design, Gate A is used as an input terminal; Source and Gate B are connected to VDD. The basic operation of the inverter is illustrated in Figure 3(a) (when the input is “Low”) and Figure 3(b) (when the input is “High”). In Figure 3(a), the voltage difference existing between the beam and Gate A creates a sufficient electrostatic force of attraction on the beam to move toward left. When the beam touches the drain terminal, it produces the output “VDD”, and it measures with respect to ground. In Figure 3(b), the output at the drain terminal is “0” as there is no voltage difference between the beam and Gate A.

3.2 XOR gate

The construction of XOR gate using NEMS device and its dimensions is shown in Figure 4 and Table I, respectively. In this design, both Gates A and B are used as an input terminals, and the source terminal is connected to VDD. When both the inputs are different (either “01” or “10”), electrostatic force of attraction is created between any of the gate terminals and the beam so that the cantilever will move toward either right or left to touch the drain terminal to produce the output “VDD”, and it measures with respect to ground. When both the inputs are same (either “00” or “11”), there is no electrostatic force. Hence, the beam will be idle, thus producing an output “0” with respect to ground.

3.3 XNOR gate

The design and dimensions of the XNOR gate using NEMS device is shown in Figure 5 and Table I, respectively. From this design, it has a similar structure as XOR gate, but the electrical interconnects are changed. In this logic gate, input B is given in a complemented form by using an Inverter shown in Figure 5. When both the inputs are different “01” (“10”), the output is “0’”due to the complemented form of input B. As there is no electrostatic force of attraction between gate terminals and the beam, the beam deflection is zero. When both the inputs are same as “00” (11), the inputs are changed as “01” (“10”), it will lead to generate the electrostatic force of attraction between any of the gate terminal and the beam. Hence, the cantilever beam will move toward the right or left to touch drain terminal and provide output “VDD” with respect to ground.

3.4 NAND gate

The NAND gate is implemented using NEMS structure as shown in Figure 6, and its dimensions are given in Table I. In this design, the cantilever beam is purposely placed very near to input A. The basic operation of the NAND gate can be illustrated as follows. If both inputs are “low”, the cantilever beam deflects toward the output terminal to produce output as VDD with respect to the ground. If only one of the inputs either A or B is “low”, the cantilever beam will move toward the right or left to touch the drain terminal and provide output “VDD” with respect to ground. Finally, when both inputs are “high”, inputs A and B cannot produce adequate amount of electrostatic force to touch the output terminal; therefore, it produces an output “0” with respect to ground.

3.5 OR gate

The OR gate is implemented using NEMS switches as shown in Figure 7, and its dimensions are given in Table I. Figure 7 shows top view of the OR gate which consists of cantilever beam, two gate electrodes and output. The output is insulated from the cantilever beam, and it is placed exactly at the tip of the cantilever beam, and the cantilever beam is purposely placed very near to the gate electrode A to realize OR gate. On account of such realization, the cantilever remains stationary when A and B is 00, and hence the output pad exports “0” with respect to ground. When AB is 01 or 10, the cantilever beam is deflected toward the high input side, and output terminal makes the connection with them and the output is “1” with respect to ground. When both inputs are high, input A gate terminals generate strong electrostatic force due to short distance between input A and cantilever beam, and output terminal is shorted with input A and “1” appears at the output terminal with respect to ground.

3.6 AND/NOR gate

The device is proposed to implement the AND and NOR logic gates in the same structure, which comprises four input gate electrodes (two for each gate), cantilever beam and two output terminals [One for AND gate (O1) and other one (O2) for NOR gate] whose dimensions are given in Table I. The truth table of each logic gate is demonstrated in Table II where the logic “1” represent the deflection of cantilever beam and connect with output, while logic “0” represent no connection with output implying no deflection of the cantilever (Figure 8).

4. Analytical modeling of nanoelectromechanical system switch

According to the Euler–Bernoulli’s beam equation (Dadgour et al., 2010a, 2010b), the deflection of a cantilever beam (Source) at any moment of time along its length y (x,t) is related to the electrostatic force of attraction Fe(x,t). The Bernoulli’s equation is given by:

(1) ρA2y(x,t)t2+2x2(EI2y(x,t)x2)=Fe(x,t)
where E and I represent the Young’s modulus and moment of inertia of the beam, ρ is the mass density and A denotes the cross-sectional area of the beam.

From Figure 9, it can be observed that the displacement between the beam and the Gate B with respect to location x and time t is G–y(x,t). The electrostatic force between beam and electrodes can be calculated using parallel plate capacitance model as given in equation (2):

(2) Fe(x,t)=12ε0V2wL(Gy(x,t))2=ψ(Gy(x,t))2where(ψ=ε0V2wL2)
where L is the length of the Gate electrode, w is the width of the beam, G is the gap between Gate and Source and V is the applied voltage.

Using static switching process, the combined equations (1) and (2) can be modified into x and t dependency as given in equations (3a) and (3b):

(3a) EI4y(x)x4=ψ(Gy(x))2
(3b) ρA2y(t)t2=ψ(Gy(t))2

The solution of equation (3a) requires four boundary conditions of fixed-free beam which are specified in equation (4). The first and second boundary condition in equations (4) and (11) implies that the fixed end of the beam does not experience any deflection and its derivative is zero at the fixed end. The third and fourth boundary condition in equation (4) implies that the bending moment and shear force at the free end of the beam is zero. The third boundary condition in equation (11) implies that the deflection of the beam is equal to ε(small air gap) at x = L, and the last boundary condition implies that the derivative of the deflection function is zero at x = L. The boundary conditions in equations (4) and (7) are used to find out the pull-in analysis and pull-out analysis of the beam, respectively:

(4) y(x=0)=0y(x=0)x=02y(x=L)x2=03y(x=L)x3=0}

The assumed solution to the equation (3a) is obtained from Dadgour et al. (2010a, 2010b) and is given by equation (5):

(5) y(x)=p0+p1x+p2x2+p3x3+p4x4+p5x5+p6x6
where the coefficients p0, p1, p2, p3, p4, p5 and p6 have to be obtained using boundary conditions given in equation (4).

The Taylor series expansion of right-hand side in equation (3a) is given as:

(6) ψ(Gy(x))2=ψ[1(Gp0)2+2p1(Gp0)3x+12(4p2(Gp0)3+6p12(Gp0)4)x2]

The left-hand side of the equation (3a) can be rewritten by considering equation (5) as:

(7) EI4y(x)x4=24p4+120p5+360p6x2

By equating equations (6) and (7), we get:

(8) 24p4=ψ(Gp0)2120p5=2p1ψ(Gp0)3360p6=ψ2(4p2(Gp0)3+6p12(Gp0)4)}

Applying boundary conditions to equation (5):

(9) p0=0p1=02p2+6p3L+12p4L2+20p5L3+30p6L4=06p3+24p4L+60p5L2+120p6L3=0}

By substituting equations (8) and (9) in equation (5), the deflection of the cantilever (Source) is found to be:

(10) y(x)=GψL24G3ψL4x2+G2ψ2L512G5ψL72G718G4ψL4x3+ψ24G2x4+ψ2L2180G2(4G3ψL4)x6

Using equation (10), the pull-in voltage of the beam can be estimated.

When the cantilever beam (source) is in contact with the drain, the source is said to be in fixed–fixed condition, whose boundary conditions are given by equation (11):

(11) y(x=0)=0y(x=0)x=0y(x=L)=ζy(x=L)x=0}
where ζ is a small positive value.

The voltage required to pull-out the beam back to the original position from the drain terminal is called pull-out voltage Vpull-out. To compute Vpull-out, apply fixed–fixed boundary condition to equation (5).

Applying boundary conditions in equation (11) to equation (5) gives:

(12) p0=0p1=0p0+p1L+p2L2+p3L3+p4L4+p5L5+p6L6=ζp1+2p2L+3p3L2+4p4L3+5p5L4+6p6L5=0}

By substituting equations (8) and (12) in equation (5), the deflection of the cantilever (Source) is found to be:

(13) y(x)=72G3ζ+GψL4240G3L28L6+4ψx2+39ψ2L1020ψ2L412960G4L6ψ1380G3ψL672GL6ψ21600G5L2720L6ψG2+360ψG2x3+ψ24G2x4+72G2ζψ+ψ2L443200G5L2+720ψG2−1440L6ψG2x6

Using equation (13), the pull-out voltage of the beam can be estimated.

The transient analysis of the NEMS switch can be obtained using equation (3b) by considering y(t) as auxiliary variable as given in equation (14):

(14) y(t)=u(t)t2u(t)t2=y(t)ut·u(t)t=y(t)u(t)·y(t)}

Substituting equation (3b) in equation (14):

(15) ρA2y(t)t2=ψ(Gy(t))2=y(t)u(t)·y(t)=ψ/ρA(Gy(t))2y(t)dy=ψ/ρA(Gy(t))2u}

Equation (15) is a first-order differential equation, and its solution is given by:

(16) 12C1[(Gy(t))(ψ/ρAC1G+u(t))ψC1tan1((Gy(t))(ψ/ρAC1G+u(t))ψ/ρAC1+Gu(t))]=t+C2
where t is the intrinsic delay of the NEMS switch when the beam attains pull-in condition. The integration constants C1 and C2 are found using the boundary conditions given in equations (17) and (18):
(17) u(t=0)=0C2=0
(18) y(t)=u(t=0)t=0C1=ψρAG

The boundary condition in equation (17) implies that beam is not deflected at t = 0, and the boundary condition in equation (18) implies that rate of change of deflection is zero at t = 0.

5. Numerical simulation

The NEMS-based logic gates described in the previous section is designed and simulated using finite element MEMS computer aided design (CAD) tool Coventorware using custom fabrication process steps. The fabrication process flow for the device is given in Figure 10. In the fabrication process, 0.3 μm thick silicon dioxide (SiO2) layer is deposited on silicon wafer, followed by the deposition of 0.2 μm thick polysilicon layer. Silicon dioxide and polysilicon layers are patterned and etched to form Gate A, Gate B, Source and drain elements. Then the metallic layer is selectively patterned to form the lateral electrical contacts. Finally, source was released by removing the silicon dioxide through trench-etching process.

For finding the mechanical and electrical characteristics of the NEMS logic gates, the electro-mechanical analysis is carried out in Co-SolveEM Solver tool of COVENTORWARE which performs coupled mechanical and electrostatic analysis. The 3D structure of the proposed design is modeled by coupling the process steps from process editor, and mask layers are created in layout editor. The structure is meshed using tetrahedron parabolic meshing with an element size of 10 μm. Table I gives dimensions of the proposed NEMS logic gates design, while Table III provides the material properties of the polysilicon used in simulation. The 3D model of the inverter designed and developed by defining a process step in Coventorware is shown in Figure 11(a), and the meshed model is shown in Figure 11(b).

The modeling of an electro-static actuation requires the study of coupled behavior of electrical and mechanical. The mechanical boundary condition in the numerical modeling is that the source, drain and gate electrodes are fixed in all directions. The electrical boundary condition, potential value is given to the source and the gate electrodes of the NEMS logic gates depending on binary input conditions. State transition is the key factor for the feasibility of digital IC devices. Here, the state transition is accomplished by the deflection of the cantilever beam to connect the output terminal for different binary inputs.

6. Results and discussion

To investigate the performance of the NEMS logic gates, simulation is carried out using CosolveEM solver in Coventorware. The pull-in voltage and pull-out voltage are the most important design parameters (Boloni et al., 2010) for mechanical logic device. The deflection of the cantilever beam with applied voltage is estimated through numerical simulation using Coventorware.

The proposed logic gates are analyzed for both pull-in and pull-out characteristics which are found out through pull-in and lift-off analysis of CoSolveEM solver in Coventoware. The CoSolveEM solver comprises MemMech Solver and MemElectro Solver. The MemMech Solver provides the mechanical solution, while the MemElectro Solver gives electrostatic solution.

Pull-in analysis is performed by linearly increasing the voltage from 0 to 5 V; hence, the beam deflects to reach the output. Figure 12 shows the pull in analysis of XOR gate. At binary condition “01”, the linearly increasing voltage of 0 to 5 V is given through input “B” gate electrode which makes the cantilever beam to deflect from its standstill position to the output according to the given voltage due to electrostatic actuation between cantilever beam and Gate A and vice versa happens when binary condition is “10”. For binary “00” and “11” condition, there is no deflection of the cantilever beam due to zero electrostatic actuation between the beam and gate electrodes; hence, there is no requirement to perform the pull-in analysis. In the same way, the pull-in analysis of all the gates with their binary conditions is found out, and its values are listed out in Table IV.

An opposite effect occurs in the pull-out analysis by linearly decreasing the voltage from its pull-in voltage to 0 V. Pull-out analysis is performed by linearly decreasing the voltage from 5 V (or pull-in voltage of the respective binary conditions) to 0 V; hence, the beam releases from the output. Figure 13 shows the pull out analysis of XOR gate. At binary “01” condition, the linearly decreasing voltage of 5 to 0 V is given through input “B” gate electrode; hence, the cantilever beam deflects from its output according to the given voltage due to electrostatic actuation between cantilever beam and Gate A and vice versa takes place in the “10” condition. The pull-out analysis is found out to be 2.5 V to reach its standstill position for both “01” and “10” conditions. For binary “00” and “11” condition, the cantilever beam does not move because of zero electrostatic actuation between beam and gate electrodes; hence, the pull-out analysis is not required to be performed. In the same way, the pull-out analysis of all the gates with their binary conditions is found out, and its values are listed out in Table V.

The numerical simulation results of pull-in and pull-out analysis are compared with analytical results obtained using equations (10) and (13) as shown in Figures 12 and 13, respectively. The numerical simulation results are in close agreement with the analytical results. The error analysis for pull-in and pull-out voltage with respect to displacement is estimated, and the maximum displacement error is found out to be 0.12 per cent.

The simulation is performed by applying all the combinations of binary input signals to the respective gate electrodes. The binary “1” output condition occurs when the cantilever beam touches the output terminal due to input signals given in the gate electrodes and the binary, “0” output condition occurs when they are not contact each other. To examine the state transition for all logic gates, different binary code is applied and corresponding results are shown in Figures 14-18.

The change in capacitance value due to binary input condition for all the logic gates is performed using CoSolveEM solver tool of Coventoware. The electrostatic solution is given by the MemElectro Solver by solving for the charge and capacitance interaction between the cantilever beam, gate electrodes, output and ground. During the computation, the MemElectro Solver computes the charge on each surface and provides a final solution using boundary element method where the charge distribution is calculated for all the components by varying the applied voltage and computes the capacitance matrix using equation (19). The capacitance matrix gives values of capacitance in picofarad (pF).

(19) Q=CV

According to the binary input conditions, the capacitance value will be changed. An inverter produces a constant value when the input is “1” due to stand still condition of cantilever beam, and there is a change in capacitance value for input “0” condition due to deflection of cantilever beam caused by electrostatic actuation between beam and gate “A” electrode, and its demonstration is shown in Figure 19. Similarly, the capacitance effect of all the logic gates with their binary conditions is found out and is shown in Figure 20 to 24. These results are obtained using MemElectro solver in Coventorware. The transient analysis for the NEMS switch is carried out using equations (16)-(18), and rise time is found to be 34 µs, and the result is shown in Figure 25. The maximum power consumption of each logic gates is computed and listed in Table VI.

7. Conclusion

In this paper, NEMS logic gates using laterally actuated double-electrode NEMS structures that can implement logic functions similar as logic devices are designed, and its numerical simulations with analytical modeling are presented. The numerical simulation results are too close with the analytical modeling results. The operating voltage of the proposed NEMS logic gates is 5 V, and it can be modified by changing the dimensions according to the applications. The design can be fabricated using the custom-made foundry process. The unique feature of these logic gates is that the basic NEMS switches are modified in the mechanical structure to function as specific logic gates depending on the bias conditions of electrical interconnects. The proposed NEMS logic gates design simplifies the realization of arithmetic circuits such as adders and multiplexers.

Figures

Laterally actuated double-gate NEMS switch (a) top view (b) operation of NEMS structure in configuration-I, (c) operation of NEMS structure in configuration-II

Figure 1.

Laterally actuated double-gate NEMS switch (a) top view (b) operation of NEMS structure in configuration-I, (c) operation of NEMS structure in configuration-II

Inverter gate based on laterally actuated double-gate NEMS structure

Figure 2.

Inverter gate based on laterally actuated double-gate NEMS structure

Operating principle of Inverter gate based on laterally actuated double-gate NEMS structure

Figure 3.

Operating principle of Inverter gate based on laterally actuated double-gate NEMS structure

XOR gate based on laterally actuated double-gate NEMS structure

Figure 4.

XOR gate based on laterally actuated double-gate NEMS structure

XNOR gate based on laterally actuated double-gate NEMS structure

Figure 5.

XNOR gate based on laterally actuated double-gate NEMS structure

NAND gate based on laterally actuated double-gate NEMS structure

Figure 6.

NAND gate based on laterally actuated double-gate NEMS structure

OR gate based on laterally actuated double-gate NEMS structure

Figure 7.

OR gate based on laterally actuated double-gate NEMS structure

AND/NOR gate based on laterally actuated double-gate NEMS structure

Figure 8.

AND/NOR gate based on laterally actuated double-gate NEMS structure

Electrostatic field along the length of the beam

Figure 9.

Electrostatic field along the length of the beam

Fabrication process steps

Figure 10.

Fabrication process steps

(a) 3D model of inverter; (b) 3D meshed model of inverter

Figure 11.

(a) 3D model of inverter; (b) 3D meshed model of inverter

Comparison between the numerical and analytical simulation for calculating vpull-in for inverter, XOR and XNOR gates

Figure 12.

Comparison between the numerical and analytical simulation for calculating vpull-in for inverter, XOR and XNOR gates

Comparison between the numerical simulation and analytical simulation for calculating vpull-out for inverter, XOR and XNOR gates

Figure 13.

Comparison between the numerical simulation and analytical simulation for calculating vpull-out for inverter, XOR and XNOR gates

Numerical simulations (Coventorware) of state transitions for inverter

Figure 14.

Numerical simulations (Coventorware) of state transitions for inverter

Numerical simulations (Coventorware) of state transitions for XOR and XNOR gate

Figure 15.

Numerical simulations (Coventorware) of state transitions for XOR and XNOR gate

Numerical simulations (Coventorware) of state transitions for NAND gate

Figure 16.

Numerical simulations (Coventorware) of state transitions for NAND gate

Numerical simulations (Coventorware) of state transitions for OR gate

Figure 17.

Numerical simulations (Coventorware) of state transitions for OR gate

Numerical simulations (Coventorware) of state transitions for AND/NOR gates

Figure 18.

Numerical simulations (Coventorware) of state transitions for AND/NOR gates

Capacitance effect for inverter

Figure 19.

Capacitance effect for inverter

Capacitance effect for XOR gate

Figure 20.

Capacitance effect for XOR gate

Capacitance effect for XNOR gate

Figure 21.

Capacitance effect for XNOR gate

Capacitance effect for NAND gate

Figure 22.

Capacitance effect for NAND gate

Capacitance effect for OR gate

Figure 23.

Capacitance effect for OR gate

Capacitance effect for AND/NOR logic gate

Figure 24.

Capacitance effect for AND/NOR logic gate

Capacitance effect for OR gate

Figure 25.

Capacitance effect for OR gate

Dimensions of proposed logic gates

Description Dimensions (nm) for logic gates
Inverter, XOR and XNOR NAND OR AND/NOR
Length of the source terminal (cantilever beam) 350 350 350 350
Width of the source (cantilever beam) 25 25 25 25
Length of the gate electrodes 200 200 200 80
Width of the gate electrodes 25 25 25 25
Length of the drain terminal (output) 125 125 52.5 125
Width of the drain terminal (output) 25 25 25 25
Gap between gate electrode A and source (cantilever beam) 25 15 10 25
Gap between gate electrode B and source (cantilever beam) 25 35 12.5 25
Length of the ground terminal 125 125 125 125
Width of the ground terminal 25 25 25 25

Truth table for AND/NOR logic gate

A B O1 O2
0 0 1
0 1 0 0
1 0 0 0
1 1 1 0

The material properties and geometry used for NEMS switch

Property Value
Young’s Modulus (E) 1.62 × 105 MPa
Poisson’s ratio (ν) 0.22
Thermal expansion coefficient (K) 4.7 × 10−6 K−1
Electrical conductivity (σ) 0.05 MS/µm

Pull-in analysis of logic gates

Binary conditions XOR gate XNOR gate NAND gate OR gate AND/NOR gate
00 NA 5V 3.5V NA 5V
01 5V NA 6.5V 3.5V NA
10 5V NA 6.5V 3V NA
11 NA 5V NA 3V 5V
Note:

*NA – Not applicable

Pull-out analysis of logic gates

Binary conditions XOR gate XNOR gate NAND gate OR gate AND/NOR gate
00 NA 2.5V 1.75V NA 2.5V
01 2.5V NA 3.25V 1.75V NA
10 2.5V NA 3.25V 1.5V NA
11 NA 2.5V NA 1.5V 2.5V

Note: *NA-Not applicable

Power consumption of all logic gates

Logic gates Maximum power consumption (0.5 CV2f) in µW
Inverter 22.79805
XOR Gate 22.79805
XNOR Gate 22.79805
NAND Gate 41.68471
OR Gate 7.139452
AND/NOR Gate 18.454048

References

Abele, N., Fritschi, R., Boucart, K., Casset, F., Ancey, P. and Ionescu, A.M. (2005), “Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor”, Proceedings IEEE International Electron Devices Meeting, (IEDM Technical Digest), Washington, DC, pp. 479-481.

Boloni, F., Benabou, A. and Tounzi, A. (2010), “Comparison of pull-in voltages in MEMS using 3D FEM and analytical approaches”, COMPEL – The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol. 29 No. 6, pp. 1653-1661.

Chakraborty, S. and Bhattacharyya, T.K. (2010), “Development of MEMS based universal gate for signal processing circuit in low frequency sensor applications”, Proceedings IEEE Students’ Technology Symposium, IIT, Kharagpur, pp. 129-136.

Dadgour, H.F., Hussain, M.M. and Banerjee, K. (2010a), “A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS”, Proceedings ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), Austin, TX, pp. 7-12.

Dadgour, H.F., Hussain, M.M., Smith, C. and Banerjee, K. (2010b), “Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS”, Proceedings 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, pp. 893-896.

Johnstone, R.W., Ko, K.F., Yang, J.C., Parameswaran, M. and Erhardt, L.S. (2002), “The effects of proton irradiation on electrothermal micro-actuators”, Canadian Journal of Electrical and Computer Engineering, Vol. 27 No. 1, pp. 3-5.

Keimel, C., Claydon, G., Li, B., Park, J.N. and Valdes, M.E. (2012), “Microelectromechanical-systems-based switches for power applications”, IEEE Transactions on Industry Applications, Vol. 48 No. 4, pp. 1163-1169.

Lee, S.W., Johnstone, R. and Parameswaran, A.M. (2005), “MEMS mechancial logic units: design and fabrication with micragem and polymumps”, Proceedings Canadian Conference on Electrical and Computer Engineering, Saskatoon, pp. 1513-1516.

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Parsa, R., Lee, W.S., Shavezipur, M., Provine, J., Maboudian, R., Mitra, S., Wong, H.S.P. and Howe, T.R. (2013), “Laterally actuated platinum-coated polysilicon NEM relays”, Journal of Microelectromechanical Systems, Vol. 22 No. 3, pp. 768-778.

Peschot, A., Qian, C. and Liu, T.-J.K. (2015), “Nanoelectromechanical switches for low-power digital computing”, Micromachines, Vol. 6 No. 8, pp. 1046-1065.

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Further reading

Akarvardar, K., Elata, D., Howe, R.T. and Wong, H.-S.P. (2008), Energy-Reversible Complementary NEM Logic Gates, Santa Barbara, CA, pp. 69-70.

Akarvardar, K., Elata, D., Parsa, R., Wan, G.C., Yoo, K., Provine, J., Peumans, P., Howe, R.T. and Wong, H.-S.P. (2007), “Design considerations for complementary nanoelectromechanical logic gates”, Proceedings IEEE International Electron Devices, Washington, DC, pp. 299-302.

Chen, C., Parsa, R., Patil, N., Chong, S., Akarvardar, K., Provine, J., Lewis, D., Watt, J., Howe, R.T., Wong, H.-S.P. and Mitra, S. (2010), “Efficient FPGAs using nanoelectromechanical relays”, Proceedings FPGA’10, Monterey, CA, pp. 273-282.

He, T., Yang, R., Rajgopal, S., Bhunia, S., Mehregany, M. and Feng, P.X.-L. (2013), “Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches”, Proceedings NEMS2013, pp. 554-557.

Houri, S., Valentian, A. and Fanet, H. (2013), “Comparing CMOS-based and NEMS-based adiabatic logic circuits”, Lecture. Notes Computer. Science, Vol. 7948, pp. 36-45.

Kloub, H.A., Smith, C.E. and Hussain, M.M. (2011), “Multi states electromechanical switch for energy efficient parallel data processing”, Proceedings Saudi International Electronics, Communications and Photonics Conference (SIECPC), Saudi, pp. 9-11.

Lee, D., Lee, W.S., Chen, C., Fallah, F., Provine, J., Chong, S., Watkins, J., Howe, R.T., Wong, H.-S.P. and Mitra, S. (2013), “Combinational logic design using six-terminal NEM relays”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32 No. 5, pp. 653-666.

Ranganathan, V., He, T., Rajgopal, S., Mehregany, M., Feng, P.X.-L. and Bhunia, S. (2013), “Nanomechanical non-volatile memory for computing at extreme”, Proceedings IEEE/ACM International Symposium on Nanoscale Architectures, Brooklyn, NY, pp. 44-45.

Talukdar, A., Khan, Y. and Sultana, M. (2011), “Architectural demonstration of single pole quad throw (SPDT) MEMS switch”, Canadian Journal on Electrical and Electronics Engineering, Vol. 2 No. 4, pp. 124-129.

Supplementary materials

COMPEL_37_1.pdf (51.7 MB)

Corresponding author

G. Uma can be contacted at: guma@nitt.edu

About the authors

P. Pandiyan was born in Aruppukottai, Tamil Nadu, India, in 1985. He received the Bachelor’s Degree in Electrical and Electronics Engineering from Anna University, Chennai, India, in 2006; Master’s Degree in the Department of Electronics and Communication Engineering from Sathyabama University, Chennai, India, in 2010. He is currently working as an Assistant Professor in Electrical and Electronics Engineering Department at Sri Ramakrishna Institute of Technology, Coimbatore and also toward PhD Degree in the Department of Instrumentation and Control Engineering, National Institute of Technology, Tiruchirappalli, India. His research interests include design and simulation of MEMS based logic devices.

G. Uma was born in Madurai, Tamil Nadu, India, in 1967. She received the Bachelor’s Degree in instrumentation and control engineering from the Government College of Technology, Coimbatore, India, in 1989; the Master’s Degree in instrumentation engineering from the Madras Institute of Technology, Anna University, Chennai, in 1992; and the PhD Degree in instrumentation and control from the National Institute of Technology, Tiruchirappalli, India, in 2009. She worked as a teaching Research Fellow in Madras Institute of Technology, Anna University, Chennai, from 1990 to 1993, and worked as a Senior Technical Officer in the Department of Science and Technology sponsored project “Development of cross correlation flow meter” in Madras Institute of Technology, Anna University, Chennai, from 1993 to 1994. She worked as a Head of the Department of Instrumentation and Control Engineering, Sethu Institute of Technology, Madurai, from 1995 to 1999. She joined the Department of Instrumentation and Control Engineering as a faculty member, National Institute of Technology, Tiruchirappalli, India, in 1999, where she is currently working as an Associate Professor. Her research interests include design and development of instrumentation systems, MEMS and process control. In 2001, Dr Uma received a Young Scientist fellowship from Tamil Nadu State Council for Science and Technology under which she worked in the Thin Film Laboratory, Department of Instrumentation, Indian Institute of Science, Bangalore.

M. Umapathy was born in Ramanathapuram, Tamil Nadu, India, in 1967. He received the Bachelor’s Degree in instrumentation and control engineering from the Government College of Technology, Coimbatore, India, in 1988; the Master’s Degree in precision engineering and instrumentation from the Indian Institute of Technology Madras, Chennai, in 1990; and the PhD Degree in systems and control engineering from the Indian Institute of Technology Bombay, Mumbai, in 2001. He worked as a Graduate Engineer Trainee in NLC Limited, Neyveli, India, for a year and served as Scientist in DRDO, Government of India, Pune, India for six years. He joined the National Institute of Technology as a faculty member, Tiruchirappalli, India, in 1996, where he is currently working as a Professor in the Department of Instrumentation and Control Engineering. His research interests include smart structure modeling and control, smart materials, MEMS and interval analysis.