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The purpose of this paper is to study the high-frequency impacts of fast switching wide-bandgap transistors on electronic and motor designs. The high-frequency power converters, dedicated to driving high-speed motors, require specific models to design predictively electronic and motors.

From magnetic and electric models, the high-frequency parasitic elements for both electronics and motor are determined. Then, high-frequency circuit models accounting for of parasitic element extractions are built to study the wide bandgap transistors commutations and their impacts on motor windings.

The results of the models, for electronics and motors, are promising. The high-frequency commutation cell study is used to optimize the layouts and to improve the commutation behaviours and performances. The impact of the switching speed is highlighted on the winding voltage susceptibility. Then, the switching frequency and commutation rapidity can be both optimized to increase the performance of motor and electronics. The electronic model is validated by experimentations.

The method can be only applied to the existing motor and electronic designs. It is not taken into account in an automized global high-frequency optimizer.

Helped by magnetic and electric FEA calculations where the parasitic element extractions are performed. The switching frequency and commutation rapidity can be both optimized to increase the performance of motor and electronics.

The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay.

The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node.

This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out.

The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

The purpose of this paper is to derive the small-signal/canonical model derivation of the high-side active clamp forward converter (ACFC) with diode rectification for ideal and with resistive parasitics. It also covers the analysis of ACFC small-signal model with resistive parasitics using computer-aided modeling software Personal Computer Simulation Program with Integrated Circuit Emphasis (PSPICE) 16.6. The effects of variation of system parameters on the ACFC’s state transfer functions and operations have been highlighted in this paper.

The large-signal model and small-signal model of the ACFC with diode rectification has been derived using AC small-signal modeling approach.

The operating point of the converter changes with the consideration of resistive parasitics compared with the ideal case. The response obtained from the hardware matches with the time domain response of the averaged model and switch model developed in PSPICE.

This paper limits the study of ACFC small-signal behavior by using computer-aided design software PSPICE. The dead time of the converter is not considered because it is negligible when compared with the on and off time. The leakage inductance which plays a role in zero voltage switching of the ACFC switches is neglected in the analysis as it is very small compared to the magnetizing inductance. The switching losses are not considered in the modeling.

The mathematical computation of deriving the system transfer functions from canonical model is complex and time consuming.

The modeling with resistive parasitics improves the effectiveness of the equivalent model. Also, the analysis with computer-aided modeling software PSPICE gives reliable results in less time.

This chapter utilises the analogy of ‘parasitical resistance’ (Fisher, 2020) to explore how young people act and interact in ‘adult’ contexts, where they are welcome as young people but still subordinated because of their age, and sometimes their gender. The analysis of young people’s participation in the Greater Manchester Youth Combined Authority suggests that young people who participate in formal, adult spaces need to be able to find the ‘play in the system’ to be heard and to be involved in decision-making. In this sense, the young people embraced a form of ‘parasitism’ and developed tactics to ‘effect subversion from within hegemonic structures’ (Fisher, 2020). This new paradigm argues that resistance is less likely to be found in a radical activism now and is more likely to be found instead in the mutually exploitative relations between dominant hosts (in this case, ‘adults’) giving of their power just enough, and ‘parasitical’ actors (in this case, young people) taking only as much as they need for their own ends. The chapter does not argue that young people are ‘parasites’ at the adult table but, rather, it acknowledges young people must find ways to ‘play the game’ in spaces where longstanding tools of radical resistance have limited effect. The ‘play’ is not unproblematic, however, and the chapter concludes that young people need more than just ‘being heard’ and contributing to something that is achievable, but not especially disruptive or redistributive. Instead, involvement of young people should be focused on achieving genuine parity that can benefit as many marginalised and precarious young people as possible.

The purpose of this paper is to find a simpler model for the reactance components in the high-frequency range on the premise of ensuring the accuracy.

In this paper, based on the fractional calculus theory and the traditional integer-order model, a reactance model suitable for high frequency is constructed, and the mutation cross differential evolution algorithm is used to identify the parameters in the model.

By comparing the integer-order model, high-frequency fractional-order model and the actual impedance characteristic curve of inductance and capacitance, it is verified that the proposed model can more accurately reflect the high-frequency characteristics of inductance and capacitance. The simulation and experimental results show that the oscillator constructed based on the proposed model can analyze the frequency and output waveform of the oscillator more accurately.

The model proposed in this paper has a simple structure and contains only two parameters to be identified. At the same time, the model has high precision. The fitting errors of impedance curve and phase-frequency characteristic curve are less than 5%. Therefore, the proposed model is helpful to improve the simplicity and accuracy of circuit system analysis and design.

The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies.

The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results.

The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample.

The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

The flexibly thin film grid pressure sensor is mainly used to detect the interface pressure distribution between touching objects. Aim at larger measurement error, the strip double sensing layer pressure sensor are designed and fabricated and tested.

Defects and characteristic of the flexibly thin film grid pressure sensor based on piezoresistive effect are analyzed and pointed out in this paper. After comparison of four sensors, the strip double sensing layer pressure sensor was thought to be best.

Experiment shows that the strip double sensing layer pressure sensor could eliminate the measurement error basically and illustrates the validity of measuring the interface pressure distribution between area touching objects.

In this paper, only the strip double sensing layer pressure sensor was used to verify the validity of measuring the static interface pressure distribution between peach and platform. But there also exists some problems such as the adhering reliability of electrode and the unevenness of sensing layer. These problems could be overcome in the future research if the fabricating procedure and ingredient of material could be adjusted correctly.

The strip double sensing layer pressure sensor could be applied to detect the static interface pressure distribution such as peach pressure distribution. For dynamic measurement, this research needs to be done further.

Strip double sensing layer pressure sensor with simple “interlayer” structure and with low manufacture cost is presented to basically eliminate the measurement error of interface pressure distribution of original sensor.

This paper aims to propose a simplified model of vanadium redox flow batteries (VRBs) for VRB energy storage system (ESS) design considering the operational characteristics of VRB, and a VRB ESS, considering the low terminal voltage of VRB, was presented.

According to the designed topology of VRB ESS and the simplified model of VRB, a small perturbation analysis method was used to establish the transfer function of VRB ESS, and the controller parameters of VRB ESS under constant charging and discharging current were designed.

Test results have demonstrated that this designed VRB ESS has fast response, small overshoot, strong adaptation and high steady precision, which strongly verified the reasonable design.

This simplified model of VRB can be suitably used for VRB ESS design. This designed VRB ESS realized the bidirectional power flow of VRB and AC grid. In this designed VRB ESS, phase-shifted full-bridge converter and a single-phase inverter were used and VRB was charged and discharged under constant current.

The paper presents a topology of VRB ESS which can realize the bidirectional power flow of VRB and AC grid. Considering the complexity of VRB model, a simplified model of VRB was proposed for the controller parameters design of VRB ESS, and this method can be used in application.

This paper aims to propose an integrated protection scheme for converters of a low-power, low-cost photovoltaic system. Power electronic converters use a variety of methods to limit overload and fault current. The use of insulated and non-insulated sensors along with additional circuits to detect and limit fault current can cause current to be limited or completely cut off before damage to semiconductor devices. In addition, fuses that have slower performance are used as backup for any type of protection.

First, all the candidate points for protection are investigated. In this paper, after examining the performance of glass fuses as linear resistors, they are used as a current feedback element. A simple, isolated and reliable circuit for fault detection at various points of the system has been proposed that can be implemented and operated in single shot or auto-reclose operating mode.

The experimental results of this circuit on a dc/dc converter and an H-bridge inverter show that it can cut off all instantaneous short circuit errors in less than 50 µs and prevent damage to the semiconductor switch.

In low-cost and low-power converters, it is usually not cost-effective to use complex and expensive devices. For this reason, these converters are more vulnerable to faults. On the other hand, in complex systems such as photovoltaics, several converters are used simultaneously in different parts, and the occurrence of a fault in each of them causes the whole system to fail.