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High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

Cluster management organizations (CMOs) have emerged over the past few decades as intermediaries that support the competitiveness of place-based clusters of economic activity. Despite their economic origins, policymakers are now starting to experiment with a broader use for cluster policies that seeks to leverage CMOs to tackle societal challenges in approaches aligned with the concept of creating shared value (CSV). However, there remains a void in conceptual understanding around the specific roles that CMOs might play in overcoming the barriers faced by their members for CSV, which this paper aims to address. Bridging this gap presents an opportunity for cluster practitioners and policymakers in a context in which environmental and social sustainability are at the top of policy agendas.

Based on analysis of literature around collaborative approaches to CSV for mitigating transaction costs, the authors define the contours of a new conceptual framework for the roles that CMOs can play in fostering collective CSV. The authors illustrate how the different components of the framework are reflected in emerging cluster practice in the context of a new wave of European cluster-based projects tackling CSV elements.

The resulting framework reconciles the concepts of clusters and CSV by explicitly positioning CMOs as intermediaries for facilitating the CSV strategies of their members. CMOs embrace emergent strategy making that targets (tangible and intangible) collective CSV capabilities and addresses collective CSV challenges. Collective CSV can provide a theoretical anchor guiding future cluster policies to fully leverage the transformative potential of CMOs. This conceptual framework opens a promising empirical research agenda, particularly around evaluating the plurality of impacts of CMOs.

By stressing the social impact of CMOs alongside their well-understood economic impacts, and by enabling a categorization of functions that can support the monitoring of CMO activities toward collective CSV strategies, the framework provides a novel basis for inspiring further empirical research into the evidencing of these roles.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

As an advanced manufacturing method, additive manufacturing (AM) technology provides new possibilities for efficient production and design of parts. However, with the continuous expansion of the application of AM materials, subtractive processing has become one of the necessary steps to improve the accuracy and performance of parts. In this paper, the processing process of AM materials is discussed in depth, and the surface integrity problem caused by it is discussed.

Firstly, we listed and analyzed the characterization parameters of metal surface integrity and its influence on the performance of parts and then introduced the application of integrated processing of metal adding and subtracting materials and the influence of different processing forms on the surface integrity of parts. The surface of the trial-cut material is detected and analyzed, and the surface of the integrated processing of adding and subtracting materials is compared with that of the pure processing of reducing materials, so that the corresponding conclusions are obtained.

In this process, we also found some surface integrity problems, such as knife marks, residual stress and thermal effects. These problems may have a potential negative impact on the performance of the final parts. In processing, we can try to use other integrated processing technologies of adding and subtracting materials, try to combine various integrated processing technologies of adding and subtracting materials, or consider exploring more efficient AM technology to improve processing efficiency. We can also consider adopting production process optimization measures to reduce the processing cost of adding and subtracting materials.

With the gradual improvement of the requirements for the surface quality of parts in the production process and the in-depth implementation of sustainable manufacturing, the demand for integrated processing of metal addition and subtraction materials is likely to continue to grow in the future. By deeply understanding and studying the problems of material reduction and surface integrity of AM materials, we can better meet the challenges in the manufacturing process and improve the quality and performance of parts. This research is very important for promoting the development of manufacturing technology and achieving success in practical application.

The purpose of this study is to examine how the implementation of edge computing can enhance the progress of the circular economy within supply chains and to address the challenges and best practices associated with this emerging technology.

This study utilized a streamlined evaluation technique that employed Latent Dirichlet Allocation modeling for thorough content analysis. Extensive searches were conducted among prominent publishers, including IEEE, Elsevier, Springer, Wiley, MDPI and Hindawi, utilizing pertinent keywords associated with edge computing, circular economy, sustainability and supply chain. The search process yielded a total of 103 articles, with the keywords being searched specifically within the titles or abstracts of these articles.

There has been a notable rise in the volume of scholarly articles dedicated to edge computing in the circular economy and supply chain management. After conducting a thorough examination of the published papers, three main research themes were identified, focused on technology, optimization and circular economy and sustainability. Edge computing adoption in supply chains results in a more responsive, efficient and agile supply chain, leading to enhanced decision-making capabilities and improved customer satisfaction. However, the adoption also poses challenges, such as data integration, security concerns, device management, connectivity and cost.

This paper offers valuable insights into the research trends of edge computing in the circular economy and supply chains, highlighting its significant role in optimizing supply chain operations and advancing the circular economy by processing and analyzing real time data generated by the internet of Things, sensors and other state-of-the-art tools and devices.

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.

This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.

Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.

According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.

Surface acoustic wave (SAW) sensors have attracted great attention worldwide for a variety of applications in measuring physical, chemical and biological parameters. However, stability has been one of the key issues which have limited their effective commercial applications. To fully understand this challenge of operation stability, this paper aims to systematically review mechanisms, stability issues and future challenges of SAW sensors for various applications.

This review paper starts with different types of SAWs, advantages and disadvantages of different types of SAW sensors and then the stability issues of SAW sensors. Subsequently, recent efforts made by researchers for improving working stability of SAW sensors are reviewed. Finally, it discusses the existing challenges and future prospects of SAW sensors in the rapidly growing Internet of Things-enabled application market.

A large number of scientific articles related to SAW technologies were found, and a number of opportunities for future researchers were identified. Over the past 20 years, SAW-related research has gained a growing interest of researchers. SAW sensors have attracted more and more researchers worldwide over the years, but the research topics of SAW sensor stability only own an extremely poor percentage in the total researc topics of SAWs or SAW sensors.

Although SAW sensors have been attracting researchers worldwide for decades, researchers mainly focused on the new materials and design strategies for SAW sensors to achieve good sensitivity and selectivity, and little work can be found on the stability issues of SAW sensors, which are so important for SAW sensor industries and one of the key factors to be mature products. Therefore, this paper systematically reviewed the SAW sensors from their fundamental mechanisms to stability issues and indicated their future challenges for various applications.