Search results

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

The purpose of this paper is to design a voltage reference circuit for current source of radio frequency integrated circuit blocks. The voltage reference circuit is called voltage for current source (VCS).

The circuit concept is discussed. A voltage‐controlled oscillator (VCO) and buffer circuit together with VCS circuit are built to prove the concept. Though the VCS circuit employs no array of diode like standard bandgap circuit, it still employs the concept of proportional to absolute temperature (PTAT) and a complement to absolute temperature (CTAT) elements. The integrated VCO, together with VCO core and VCO buffer circuits, are designed for W‐CDMA application particularly for the demodulator section. All circuits are built in f_T=45 GHz SiGe BiCMOS process.

At 760 MHz the power consumption for core circuit is 0.6 and 3.3 mA for VCO buffer amplifier. The fabricated VCO circuit together with VCO buffer was tested and measured with VCO output of −6 dBm at 760 MHz with variation of 0.1 dBm across −40°C to 85°C.

A voltage reference circuit which is derived from PTAT and CTAT current generators is presented. The circuit is capable of providing a constant current across absolute temperature or a current PTAT.

Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.

This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.

As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.

Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

The purpose of this paper is to design and implement a fully integrated low‐phase noise and large tuning range dual‐band LC voltage‐controlled oscillator (VCO) in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.

Two parallel‐connected single‐band VCOs are designed to implement the proposed VCO. Adopting a simple and straight‐forward architecture, the dual‐band VCO is configured to operate at two frequency bands, which are from 1.48 GHz to 1.78 GHz and from 2.08 GHz to 2.45 GHz. A band selection circuit is designed to perform band selection process based on the controlling input signal.

The proposed VCO features phase noise of −104.7 dBc/Hz and −108.8 dBc/Hz at 1 MHz offset frequency for both low corner and high corner end of the low‐band operation. For high‐band operation, phase‐noise performance of −101.1 dBc/Hz and −110.4 dBc/Hz at 1 MHz offset frequency are achieved. The measured output power of the dual‐band VCO ranges from −8.4 dBm to −5.8 dBm and from −9.6 dBm to −8.0 dBm for low‐band and high‐band operation, respectively. It was also observed that the power differences between the fundamental spectrum and the nearby spurious tone range from −67.5 dBc to −47.7 dBc.

The paper is useful to both the academic and industrial fields since it promotes the concept of multi‐band or multi‐standard system which is currently in demand in the telecommunication industry.

The paper aims to present the novel design approach for a low power LC-voltage-controlled oscillators (VCO) design with low phase noise that too targeted at the most sought band of Bluetooth applications. Owing to their crucial role in a wide variety of modern applications, VCO and phase-locked loop (PLL) frequency synthesizers have been the subject of extensive research in recent years. In fact, VCO is one of the key components being used in a modern PLL to provide local frequency signal since a few decades. The complicated synthesizer requirements imposed by cellular phone applications have been a key driver for PLL research.

This paper first opted to present the recent developments on implemented techniques of LC-VCO designs in popular RF bands. An LC-VCO with a differential (cross-coupled) MOS structure is then presented which has aimed to compensate the losses of an on-chip inductor implemented in UMC’s 130 nm RF-CMOS process. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address the narrowband (S-Band) applications where Bluetooth has been the most sought one. The stacked inductor topology has been adopted to get the benefit of its on-chip compatibility and low noise. The active differential architecture, which basically is a cross-coupled NMOS structure, has been then envisaged for the gain which counters the losses completely. Three major areas of LC-VCO design are considered and worked upon for the optimum design parameters, which includes Bluetooth coverage range of 2.410 GHz to 2.490 GHz, better linearity and high sensitivity and finally the most sought phase noise performance for an LC-VCO.

The work provides the complete design aspect of a novel LC-VCO design for low phase noise narrowband applications such as Bluetooth. Using tuned MOS varactor, in 130 nm-RF CMOS process, a high gain sensitivity of 194 MHz/Volt was obtained. Thus, the entire frequency range of 2415-2500 MHz for Bluetooth applications, supporting multiple standards from 3G to 5G, was covered by voltage tuning of 0.7-1.0 V. To achieve the low power dissipation, low bias (1.2 V) cross-coupled differential structure was adopted, which completely paid for the losses occurred in the LC resonator. The power dissipation comes out to be 8.56 mW which is a remarkably small value for such a high gain and low noise VCO. For the VCO frequencies in the presented LO-plan, the tank inductor was allowed to have a moderate value of inductance (8 nH), while maintaining a very high Q factor. The LC-VCO of the proposed LO-generator achieved extremely low phase noise of −140 dBc/Hz @ 1 MHz, as compared to the contemporary designs.

Though a professional tool for inductor and circuit design (ADS-by Keysight Technologies) has been chosen, actual inductor and circuit implementation on silicon may still lead to various parasitic evolutions; therefore, one must have that margin pre-considered while finalizing the design and testing it.

The proposed LC-VCO architecture presented in this work shows low phase noise and wide tuning range with high gain sensitivity in S-Band, low power dissipation and narrowband nature of wireless applications.

The on-chip stacked inductor has uniquely been designed with the provided dimensions and other parameters. Though active design is in a conventional manner, its sizing and bias current selection are unique. The pool of results obtained completely preserves the originally to the full extent.

The purpose of this paper is to design a low phase noise and high figure of merit, fully integrated, voltage‐controlled oscillator (VCO) which was fabricated in TSMC CMOS 0.18‐μm 1P6M process.

A differential PMOS cross‐coupled architecture VCO with the capacitive feedback technology was designed to increase the linearity of frequency tuning range and decrease the phase noise. Varactor determining the performance of tuning range is also a key component in the design of VCO. The authors adopt the accumulation‐mode MOS varactor. The output spectrum and the phase noise are measured by E5052A spectrum analyzer.

The VCO is successfully fabricated in TSMC RF CMOS 0.18um 1P6M process. The measured tuning range is from 10.875 GHz ∼ 11.1 GHz with control voltage from 0 to 1.5 V. The measured phase noise is as low as −120.42 dBc/Hz at 1 MHz offset and the high FOM is −189.5 dBc/Hz. The output spectrum is −10.51dBm with center oscillator frequency of 10.942 GHz. The core circuit without buffer consumes power of 15 mW from a 1.8 V supply voltage.

This paper shows a fully integrated CMOS LCVCO architecture using capacitive feedback technology with low phase noise and high figure of merit for OC‐192 SONET applications.

Multiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO.

The proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance.

The introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively.

This technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.

A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P_−1dB), power dissipation and reduction of switching quad C_gs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.

A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P_−1dB in 0.18‐μm CMOS technology.

The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.

The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.

In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.

Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.

The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients.

The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches.

In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents.

The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.