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This paper aims to propose a modified full-additive method (MFAM) to fabricate fine copper lines for high density interconnection (HDI) printed circuit boards (PCBs). In addition, the surface of the fine copper lines is treated with a brown oxidation process to obtain good adhesion between the copper and the dielectric resin.

Fine copper lines fabricated by MFAM were observed to evaluate the undercut quality, in comparison to undercut quality of copper lines fabricated by the semi-additive method and the subtractive method. The effect of the thickness of the dry film on the quality of the copper plating was investigated to obtain the regular shape of fine lines. The fine copper lines treated with the brown oxidation process were also examined to generate a coarse surface microstructure to improve the adhesion between the copper and the dielectric resin. The cross section and surface of as-fabricated fine copper lines were characterized using an optical microscope, a scanning electron microscope and an atomic force microscope.

MFAM has the potential to fabricate high-performance fine copper lines for HDI PCBs. Undercut of as-fabricated fine copper lines could be prevented to meet the design requirement of impedance. In addition, fine copper lines exhibit enough adhesive force to laminate with dielectric resin after the brown oxidation process.

MFAM, with the advantages of high efficiency and being a facile process, is developed to fabricate high-quality fine copper lines for industrial HDI PCB manufacture.

Optimized plating conditions, included proper designs of insulating shield (IS), auxiliary cathode (AC) and different patterns, contribute to the uniformity enhancement of copper deposition.

Plating experiments were implemented in vertical continuous plating (VCP) line for manufacturing in different conditions. Multiphysics coupling simulation was brought to investigate and predict the plating uniformity improvement of copper pattern. In addition, the numerical model was based on VCP to approach the practical application.

With disproportionate current distribution, different plating pattern design formed diverse copper thickness distribution (CTD). IS and AC improved plating uniformity of copper pattern because of current redistribution. Moreover, optimized plating condition for effectively depositing more uniformed plating copper layer in varied pattern designs were derived by simulation and verified by plating experiment.

The comparison between experiment and simulation revealed that multiphysics coupling is an efficient, reliable and of course environment-friendly tool to perform research on the uniformity of pattern plating in manufacturing.

The purpose of this study is to investigate the synergism of convection, current density distribution and additives by numerical simulation and electrochemical experiments for good throwing power (TP) of copper electro-deposition in printed circuit board (PCB) manufacture.

The flow field of THs and current density distribution on various AR of THs are calculated and analyzed. Meanwhile, corresponding simulation is used to study the performance of plating electrolytes on TP. Two electrochemical parameters, overpotential (η) and potential difference (△η), are chosen to evaluate the electrochemical properties of different plating solutions by galvanostatic measurement and potentiodynamic cathode polarization at different rotating speeds.

By combining both the results of simulation and practical plating, these two electrochemical properties of electrolytes exhibit significant impact to the system at varied conditions. Especially, the electrolyte with higher polarizing η and △η values lead to the elevated TP for AR of more than 2:1.

The harring cell model is built as a bridge between the theoretical and experimental study for control of uniformity of plating THs in PCB manufacturing. This dual-parameter evaluation is validated to be a promising decisive method to guide the THs plating with particular AR in industry.

The purpose of this paper is to establish an accurate model to quantify the effect of conductor roughness on insertion loss (IL) and provide improved measurements and suggestions for manufacturing good conductive copper lines of printed circuit board.

To practically investigates the modified model of conductor roughness, three different kinds of alternate oxidation treatments were used to provide transmission lines with different roughness. The IL results were measured by a vector net analyzer for comparisons with the modified model results.

An accurate model, with only a 1.8% deviation on average from the measured values, is established. Compared with other models, the modified model is more reliable in industrial manufacturing.

This paper introduces the influence of tiny roughness structures on IL. Besides, this paper discusses the effect of current distribution on IL.

The purpose of this paper is to form high density interconnection (HDI) of backboard for press-fit applications with the pre-curing conditions of conductive paste. The best condition of pre-curing conductive paste should be found to obtain good electrical and physical performance of the conductive paste and avoid the simultaneous curing behavior of prepreg.

A novel structure of backboard was designed by using the connection of conductive paste-filled through holes to connect two multilayers. Pre-curing conditions of conductive paste were investigated to find their effects on resistance, bond strength and volume shrinkage. The reliability of pre-curing conductive paste was also analyzed.

Pre-curing conditions led to a great influence on the resistance, bond strength and volume shrinkage of the conductive paste. The best condition of pre-curing conductive paste was chosen as the low curing temperature of 60°C and a curing time of 30 min. Cured conductive paste exhibited square resistance of 4.205 mΩ/□ and bonding strength of 22.86 N. The as-obtained pre-curing condition could improve the reliability of conductive paste. Pre-curing process of conductive paste at extremely low temperature to interconnect two multilayer structures improved the density interconnection of backboard for press-fit applications.

The use of HDI of backboard could lead to good assembly for high-speed signal transmission of electronic products with press-fitting components. The connection of pre-curing conductive paste for multilayers could have important function for improving the application for communication backboard.

As a common transmission line, the microstrip line plays an important role in high-speed circuits. The purpose of this paper was to investigate the effects of the circuit design of microstrip lines on the signal integrity (SI). In addition, the influence of the type and thickness of the solder resist ink on SI was analyzed to provide guidance for the related producing process design of printed circuit boards (PCBs).

Microstrip line properties consisting of shape, line-width/line-space ratio, reference layer design and as-covered solder resist ink were designed to measure the insertion loss (S₂₁) in high-speed PCB.

The study showed that the insertion loss (S₂₁) of straight, meander, snake-shaped and wavy microstrip lines was approximately consistent. A microstrip line with width/space ratio less than 0.96 is necessary, as the differential line closing produces a mutual interference. Reference layer including the discontinuous area should be repaired by adjusting the microstrip line parameters. With regard to the solder resist ink, the insertion loss of novel solder resist ink decreased by 0.163 dB/in at 12.9 GHz and 0.164 dB/in at 14 GHz, compared with traditional solder resist ink. Accordingly, the insertion loss effectively improved at a lower thickness of solder resist.

This paper demonstrated that the common designing factors of line shape, line/space ratio, reference layer and solder resist influence microstrip line SI in the significant reference of designer-making PCB layout.

The purpose of this paper is to form good cutting qualities in glass-epoxy material for opening flexible areas of rigid-flex printed circuit boards (PCB) by ultraviolet (UV) laser cutting.

The cut width and cut depth of glass-epoxy materials were both observed to evaluate their cutting qualities. The heat affected zone (HAZ) of the glass-epoxy material was also investigated after UV laser cutting. The relationships between the cut width and the parameters of various factors were analyzed using an orthogonal experimental design.

The cut width of the glass-epoxy material gradually increased with the increment of the laser power and Z-axis height, while cutting speed and laser frequency had less effect on the cut width. Optimal parameters of the UV laser process for cutting glass-epoxy material were obtained and included a laser power of 6W, a cutting speed of 170 mm/s, a laser frequency of 50 kHz and a Z-axis height of 0.6 mm, resulting in an average cut width of 25 μm and small HAZ.

Flexible areas of rigid-flex PCBs are in good agreement with the cutting qualities of the UV laser. The use of a UV laser process could have important potential for cutting glass-epoxy materials used in the PCB industry.

The purpose of this paper is to form copper coin-embedded printed circuit board (PCB) for high heat dissipation.

Manufacturing optimization of copper coin-embedded PCB involved in the design and treatment of copper coin, resin flush removal and flatness control. Thermal simulation was used to investigate the effect of copper coin on heat dissipation of PCB products. Lead-free reflow soldering and thrust tests were used to characterize the reliable performance of copper coin-embedded PCB.

The copper coin-embedded PCB had good agreement with resin flush removal and flatness control. Thermal simulation results indicated that copper coin could significantly enhance the heat-dissipation rate by means of a direct contact with the high-power integrated circuit chip. The copper coin-embedded PCB exhibited a reliable structure capable of withstanding high-temperature reflow soldering and high thrust testing.

The use of a copper coin-embedded PCB could lead to higher heat dissipation for the stable performance of high-power electronic components. The copper coin-embedded method could have important potential for improving the design for heat dissipation in the PCB industry.

Pb‐free soldering challenged printed circuit board (PCB) assembly with high temperature. The purpose of this paper is to explain the failure mechanism of printed circuit board (PCB) assembly with solder bubbles of vias to avoid the problems of via‐drilling defects and solder joint failure.

The failure of PCB vias with solder bubbles was investigated through cross sections and SEM microstructure inspection, TMA measurement, moisture absorption analysis and DSC measurement. The moisture absorption and CTE of FR4 laminate matched with manufacturing requirement to avoid the effects of solder bubbles. The effects of via drilling with a dull drill bit were compared to that with a new drill bit.

The moisture absorbed inside holes of via plating layers could be exposed to induce solder bubbles during Pb‐free soldering assembly and dull drill bits should be prevented during the drilling process to avoid the no‐bearing drilling effects.

The failure of PCB vias is not only involved in the voiding in solder joints but manufacturing processes of PCB. The paper designs an approach to analyse the properties of PCB materials and the drilling effects of vias to find out the mechanism resulting in solder bubbles of vias. The problem of drill bits should be considered to prevent the moisture absorbed in drilling vias with defects.

The purpose of this paper was to present a simple and convenient technology to produce the electronic-grade CuO. The prepared electronic-grade CuO fully meets the demands of industrial production of high density interconnect (HDI).

A new method termed as open-circuit potential-time technology is proposed to measure the dissolution time of CuO in plating solution. X-ray diffraction (XRD) scanning electron microscopy (SEM) and inductively coupled plasma-atomic emission spectroscopy (ICP-AES) were used to characterize the prepared CuO. Solder shock and reflow tests were carried out to examine the Cu deposits.

All aspects of the prepared CuO meet the demands of printed circuit board (PCB) industry.

A simple and convenient technology was presented to produce the electronic-grade CuO. A new method was proposed to determine the dissolution time of CuO in plating solution.