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A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.

The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.

Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.

The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

The purpose of this paper is to study the two-dimensional micropolar fluid flow with conjugate heat transfer and mass transpiration. The considered nanofluid has graphene nanoparticles.

Governing nonlinear partial differential equations are converted to nonlinear ordinary differential equations by similarity transformation. Then, to analyze the flow, the authors derive the dual solutions to the flow problem. Biot number and radiation effect are included in the energy equation. The momentum equation was solved by using boundary conditions, and the temperature equation solved by using hypergeometric series solutions. Nusselt numbers and skin friction coefficients are calculated as functions of the Reynolds number. Further, the problem is governed by other parameters, namely, the magnetic parameter, radiation parameter, Prandtl number and mass transpiration. Graphene nanofluids have shown promising thermal conductivity enhancements due to the high thermal conductivity of graphene and have a wide range of applications affecting the thermal boundary layer and serve as coolants and thermal management systems in electronics or as heat transfer fluids in various industrial processes.

Results show that increasing the magnetic field decreases the momentum and increases thermal radiation. The heat source/sink parameter increases the thermal boundary layer. Increasing the volume fraction decreases the velocity profile and increases the temperature. Increasing the Eringen parameter increases the momentum of the fluid flow. Applications are found in the extrusion of polymer sheets, films and sheets, the manufacturing of plastic wires, the fabrication of fibers and the growth of crystals, among others. Heat sources/sinks are commonly used in electronic devices to transfer the heat generated by high-power semiconductor devices such as power transistors and optoelectronics such as lasers and light-emitting diodes to a fluid medium, thermal radiation on the fluid flow used in spectroscopy to study the properties of materials and also used in thermal imaging to capture and display the infrared radiation emitted by objects.

Micropolar fluid flow across stretching/shrinking surfaces is examined. Biot number and radiation effects are included in the energy equation. An increase in the volume fraction decreases the momentum boundary layer thickness. Nusselt numbers and skin friction coefficients are presented versus Reynolds numbers. A dual solution is obtained for a shrinking surface.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

This paper aims to investigate the influence of composite solder joint preparation on the thermal properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the mechanical strength of the soldered joint.

Reinforced composite solder joints with the addition of titanium oxide nanopowder (TiO₂) were prepared. The reference alloy was Sn99Ag0.3Cu0.7. Reinforced joints differed in the weight percentage of TiO₂, ranging from 0.125 to 1.0 Wt.%. Two types of components were used for the tests. The resistor in the 0805 package was used for mechanical strength tests, where the component was soldered to the FR4 substrate. For thermal parameters measurements, a power element MOSFET in a TO-263 package was used, which was soldered to a metal core printed circuit board (PCB) substrate. Components were soldered in batch IR oven.

Shear tests showed that the addition of titanium oxide does not significantly increase the resistance of the solder joint to mechanical damage. Titanium oxide addition was shown to not considerably influence the soldered joint’s mechanical strength compared to reference samples when soldered in batch ovens. Thermal resistance R_thj-a of MOSFETs depends on TiO₂ concentration in the composite solder joint reaching the minimum R_thj at 0.25 Wt.% of TiO₂.

Mechanical strength: TiO₂ reinforcement shows minimal impact on mechanical strength, suggesting altered liquidus temperature and microstructure, requiring further investigation. Thermal performance: thermal parameters vary with TiO₂ concentration, with optimal performance at 0.25 Wt.%. Experimental validation is crucial for practical application. Experimental confirmation: validation of optimal concentrations is essential for accurate assessment and real-world application. Soldering method influence: batch oven soldering may affect mechanical strength, necessitating exploration of alternative methods. Thermal vs mechanical enhancement: while TiO₂ does not notably enhance mechanical strength, it improves thermal properties, highlighting the need for balanced design in power semiconductor assembly.

Incorporating TiO₂ enhances thermal properties in power semiconductor assembly. Optimal concentration balancing thermal performance and mechanical strength must be determined experimentally. Batch oven soldering may influence mechanical strength, requiring evaluation of alternative techniques. TiO₂ composite solder joints offer promise in power electronics for efficient heat dissipation. Microstructural analysis can optimize solder joint design and performance. Rigorous quality control during soldering ensures consistent thermal performance and mitigates negative effects on mechanical strength.

The integration of TiO₂ reinforcement in solder joints impacts thermal properties crucial for power semiconductor assembly. However, its influence on mechanical strength is limited, potentially affecting product reliability. Understanding these effects necessitates collaborative efforts between researchers and industry stakeholders to develop robust soldering techniques. Ensuring optimal TiO₂ concentration through experimental validation is essential to maintain product integrity and safety standards. Additionally, dissemination of research findings and best practices can empower manufacturers to make informed decisions, fostering innovation and sustainability in electronic manufacturing processes. Ultimately, addressing these social implications promotes technological advancement while prioritizing consumer trust and product quality in the electronics industry.

The research shows the importance of the soldering technology used to assemble MOSFET devices.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.

This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.

Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.

According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.

This study aims to improve detection efficiency of fluorescence biosensor or a graphene field-effect transistor biosensor. Graphene field-effect transistor biosensing and fluorescent biosensing were integrated and combined with magnetic nanoparticles to construct a multi-sensor integrated microfluidic biochip for detecting single-stranded DNA. Multi-sensor integrated biochip demonstrated higher detection reliability for a single target and could simultaneously detect different targets.

In this study, the authors integrated graphene field-effect transistor biosensing and fluorescent biosensing, combined with magnetic nanoparticles, to fabricate a multi-sensor integrated microfluidic biochip for the detection of single-stranded deoxyribonucleic acid (DNA). Graphene films synthesized through chemical vapor deposition were transferred onto a glass substrate featuring two indium tin oxide electrodes, thus establishing conductive channels for the graphene field-effect transistor. Using π-π stacking, 1-pyrenebutanoic acid succinimidyl ester was immobilized onto the graphene film to serve as a medium for anchoring the probe aptamer. The fluorophore-labeled target DNA subsequently underwent hybridization with the probe aptamer, thereby forming a fluorescence detection channel.

This paper presents a novel approach using three channels of light, electricity and magnetism for the detection of single-stranded DNA, accompanied by the design of a microfluidic detection platform integrating biosensor chips. Remarkably, the detection limit achieved is 10 pm, with an impressively low relative standard deviation of 1.007%.

By detecting target DNA, the photo-electro-magnetic multi-sensor graphene field-effect transistor biosensor not only enhances the reliability and efficiency of detection but also exhibits additional advantages such as compact size, affordability, portability and straightforward automation. Real-time display of detection outcomes on the host facilitates a deeper comprehension of biochemical reaction dynamics. Moreover, besides detecting the same target, the sensor can also identify diverse targets, primarily leveraging the penetrative and noninvasive nature of light.

Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).

This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.

This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.

This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.

This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.