Search results

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.

In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.

The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.

The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

A new dual‐rail adiabatic logic family is proposed in this paper. Modified dual‐rail improved adiabatic pseudo domino logic with high throughput (MDIAPDL‐HT) is an improved adiabatic logic design aimed at low power and high throughput performance. The basic structure is the same as the MDIAPDL, but with a different clocking system. This results in power savings up to 95 percent compared to the static CMOS. It has higher throughput with a factor of about four compared to MDIAPDL and a factor of two compared to 4ϕ‐IAPDL.

An improved structure for adiabatic pseudo‐domino logic (APDL) family is presented in this paper. The modified dual‐rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.

The objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraints.

The work has been carried out in two parts. In the first part, simulation results were generated using five different architectures; each designed using four logic design styles for three different transistor sizes. The designs were simulated to generate the values of worst‐case propagation delay and energy consumption per addition. This information is used for validating the delay and energy consumption per addition in the second part.

Optimum adder design under varying condition can be found out using this work.

The predictive model does not consider the variation in load capacitance of each cell.

At present, a prime requirement in application specific integrated circuit design is reduction in design cycle time. As a result, there is minimum scope for exploration of arithmetic units in order to choose the best‐suited design. This work will help the designers to choose an optimum adder design for a given set of requirements.

In this work, four degrees of freedom are taken in adder design space, which are not taken before. Here, the adder design space has been explored, studied, and analyzed in this study under so many varying conditions.

The purpose of this paper is to revise the concept of positioning to differentiate between fundamental approaches to it and chart a scheme of schools of positioning.

An extensive literature review traces the roots and evolution of the concept. Two approaches to positioning are explored and related to the paradigms of market and brand orientation. Based on current theory and practice, different schools of positioning are identified and categorized along a market- and brand-orientation spectrum. Metaphors differentiate schools of positioning, illustrated by case examples.

Positioning is a key concept in marketing, branding and strategy. However, its theoretical and practical usefulness is in peril due to its many meanings, applications and overall vagueness. There is a need for a theoretical overview of positioning, which the literature currently lacks. Two approaches to define a brand’s position are identified and introduced: market- and brand-oriented positioning. Five principal schools of positioning show how these are different and why differentiating between them matters. The choice of school implies the market- and/or brand-oriented approach to positioning.

Further empirical case-based research might investigate when, what and how different positioning schools are applied in practice. The brief cases in this paper indicate a dynamic over time regarding the applications of the brand- and market-oriented school of positioning. An in-depth theoretical and practical investigation of the dynamics of positions would be of value for the research field.

The distinction among different schools of thought helps bridge the gap between the theory and practice of positioning. A specific positioning objective can guide management in the selection of a particular school of positioning, which enables management to make more insightful conscious choices regarding its opportunities, limitations and consequences.

Position and positioning is of relevance in society in broad terms, e.g. in sports, politics and culture. Positioning strategy is discussed and implemented in different industries (business-to-business and consumer), for all kinds of brands (including, for instance, corporate brands) and for “brands” in the very widest sense (such as places or people).

This paper relates positioning to the fundamental discussion of brand and market orientation. It integrates positioning research and provides a structured overview of the concept.

To show new design methodology of low power circuit design (Low Power Critical Voltage Transition Logic – LPCVTL) over the conventional CVTL methodology. The comparison is in terms of speed, area and power consumption.

The new design employs feedback mechanism with a different clocking methodology to overcome high static power dissipation of conventional CVTL design.

LPCVTL has lower power dissipation property as compared to the conventional CVTL design through the observation of the simulated results of an inverter chain and half adder designs. LPCVTL power dissipation is about eight times smaller than the conventional CVTL.

The desired clock frequency is limited by the output signal response.

LPCVTL is an alternative to dynamic digital IC design methodology which has high speed advantage while maintaining low power consumption.

Besides combinational circuits, sequential circuits, for instance, flip‐flops, also play an important role in the design of digital systems. In this article, energy‐recovery/adiabatic flip‐flops based on improved PAL‐2N logic with complementary pass transistor logic (CPL) evaluation tree (C‐PAL) family will be described. HSPICE simulation results show that the proposed SR and JK flip‐flops are able to achieve significant power savings compared to the conventional CMOS flip‐flops, with operating frequencies from 50MHz to 250MHz. The supply voltages are scaled down from 5V to 2.5V in order to compare the power consumption with CMOS counterpart. In addition, a 4‐bit binary counter is designed to verify the functionality of the proposed flip‐flops.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.