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Besides combinational circuits, sequential circuits, for instance, flip‐flops, also play an important role in the design of digital systems. In this article, energy‐recovery/adiabatic flip‐flops based on improved PAL‐2N logic with complementary pass transistor logic (CPL) evaluation tree (C‐PAL) family will be described. HSPICE simulation results show that the proposed SR and JK flip‐flops are able to achieve significant power savings compared to the conventional CMOS flip‐flops, with operating frequencies from 50MHz to 250MHz. The supply voltages are scaled down from 5V to 2.5V in order to compare the power consumption with CMOS counterpart. In addition, a 4‐bit binary counter is designed to verify the functionality of the proposed flip‐flops.

The purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).

In the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.

The design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.

The study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

The authors use the debates instigated by Bernal's Black Athena to rethink the concepts of “race”, “culture” and “diversity” in organization and aim to examine their intersection with academic authority.

Drawing on the works of Derrida and Hegel, the authors question the pursuit of origins and illustrate its role in essentializing race, culture and diversity. The paper examines these through binaries including white/black, nature/culture, purity/diversity and diversity/university.

First, both the Black Athena debates and the organizational literature turn to origins to ground concepts of difference. This attests to the power of narratives of descent in defining current interests. Second, organization studies have relied on images of a clear past which had eliminated racialization and its implications. Whereas culture is considered progressive, as a user‐friendly term it has served as a “surrogate” or “homologue” for race. Diversity, in turn, has been deployed both to harbour and to control difference in organization.

The Black Athena debates alert people to the authority of scholars and practitioners in normalising identity categories in organization. They challenge people to develop theories and practices of organizational diversity that are open to ongoing difference rather than essence and origin.

Derrida's contribution has rarely been used in organizational history, particularly its implication with Hegel's legacy to the historical and cultural canon. The paper invites readers to rethink the notions of race, culture and diversity by examining their historical development and considering the history of their inclusion into the canons of management and organization. Historicising can unsettle entrenched assumptions, but the cautionary word is that it can also legitimate current practices by identifying their relevance since “the beginning”.

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.

The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.

A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.

Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.

To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.

The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

The idea of intelligent agents has been around for some time now: software packages that browse online information for material of particular interest to you, the user. With the World Wide Web growing at the rate it is (the Net Happenings list, to which this reviewer subscribes, reports in the region of 150–200 new sites a week, and that is just the ones people tell it about) the concept of an army of intelligent agents doing research for you has a certain appeal.

This paper aims to examine the anatomy of a real estate bubble. In the process, the paper identifies three phases of the market's evolution: flips, flops and foreclosures. An examination of the Las Vegas real estate market illustrates the three phases.

The paper examines transaction data from the metropolitan Las Vegas area (Clark County) from 1994 to 2009. The first part of the analysis identifies the three phases of the bubble and is descriptive in nature. This is followed by more formal tests of Granger causality.

In the early part of the sample, a large percentage of transactions are speculative or “flips” causing prices to rapidly increase. Eventually, flipping loses its profitability and over the last three years, there is an increasing number of foreclosures leading to falling prices. The descriptive analysis of the Las Vegas market is augmented with causality tests which show that prices were the driving force behind all three phases in the market's evolution.

Future research might focus on underlying structural inter‐temporal relationships to augment the Granger causality tests.

Analysis shows that price is the driving force behind a bubble and that loan modification programs alone will not solve the current housing crisis.

Government entities might expand neighborhood stabilization programs to affect both demand and supply of homes. Moreover, it might be prudent to include information related to flipping on multiple listing service agreements. Additionally, local governments should be consistent in their record keeping.

To the best of the authors' knowledge, this is the first paper to examine the housing bubble using an extensive set of transaction data.

The purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).

With SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.

Simulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.

In this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

This work is intended to historically commemorate the one hundredth anniversary of the invention of a new type of electronic circuit, referred to in 1919 by Abraham and Bloch as a multivibrator and by Eccles and Jordan as a trigger relay (later known as a flip-flop).

The author also considers the circuit-technical side of this new type of circuit, considering the technological change as well as the mathematical concepts developed in the context of the analysis of the circuit.

The multivibrator resulted in a “circuit shape” which became one of the most applied nonlinear circuits in electronics. It is shown that at the beginning the multivibrator as well as the flip-flop circuits were used because their interesting properties in the frequency domain.

Therefore, it is a very interesting subject to consider the history of the multivibrator as electronic circuits in different technologies including tube, transistors and integrated circuits as well as the mathematical theory based on the concept from electrical circuit theory.