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High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

A package performance bottleneck is developing because of the inability to densely wire single chip modules together on the printed wiring board. An array processor, constructed by means of various high performance packaging techniques, demonstrates that multichip modules of even modest size can give dramatic improvements in the packaging figure of merit.

Rapid advancements in nanotechnology are going to bring radical changes in the society and particularly in wireless communication where small, smart and speedy systems are everyone's first choice. This is possible as application of nanotechnology is taking place in WiMAX/WiFi and other wireless communication systems, which is ‘State-of-the-Art’ technology at the moment. Evolution of microelectronics towards miniaturization is one of the main motivations for nanotechnology. The continued improvements in miniaturization, speed and power reduction in information processing devices, sensors, displays, logic devices, storage devices, transmission devices, etc. will bring another technical revolution, which will change our life. In our research work, we would like to focus on design and development of programmable frequency synthesizer for WiMAX/WiFi wireless communication (to the scale of < 50 nanometer). The transceiver will support fixed, portable, and mobile WiMAX operation. The design strategies focus on maximum operating frequency, low power consumption, low voltage operation, minimize number of gates/transistors, CMOS Technology (< 50 nanometer), reduced fabrication cost, high speed applications in WiMAX/WiFi/Satellite communications, flexibility, programmability, and service efficiency. The proposed ‘Programmable frequency synthesizer will be a new device with its varied application for WiMAX/WiFi/Satellite and other wireless communication systems. The transceiver will support fixed, portable, and mobile WiMAX operation.

Janette Rowland has been appointed marketing services manager of General Hybrid. Based at their facility on Tyneside, and reporting to the general sales manager, Ms Rowland is responsible for all PR, marketing support and promotional activities for General Hybrid worldwide. She joins the company from CSM, a software house, where she held the position of marketing executive.

The purpose of this paper is to use data envelopment analysis (DEA) to evaluate the efficiency of the wafer fabrication industry in Taiwan.

The input variables are total assets, operation costs, and operation expenditures, and the output variable is net sales. This study uses the Pearson correlation to indicate positively correlation between input and output variables, applies DEA to analyze the efficiency scores, and utilizes Mann‐Whitney U‐test to compare the efficiency score of stock exchange market group (SEM group) with that of over‐the‐counter market group (OTC group). Moreover, this paper explores the efficiency performance over different periods by use of the Malmquist productive Index (MPI).

This study indicates that Taiwan Semiconductor Manufacturing Corporation (TSMC) has the most relative efficiency in the wafer fabrication industry of Taiwan. In addition, this study finds out the average constant returns to scale (CRS) efficiency of the Taiwanese wafer fabrication industry from 1999 to 2003 is 84.98 per cent, and the average CRS efficiencies of all nine wafer fabrication companies are over 70 per cent. This study finds out that net sales and scale efficiency of SEM group are higher than those of OTC group. Moreover, this study shows that the main inefficient causes of four companies of SEM group except TSMC and Nanya are from the inefficiency of variable returns to scale efficiency, while the main inefficient causes of all companies of OTC group are from the inefficiency of scale efficiency. Finally, according the results of the MPI in this study, the wafer fabrication industry should introduce the new technology to improve its technology change effect.

This study provides a valuable reference for wafer fabrication companies not only in reviewing their efficiency, but also in enhancing their operational performance.

To provide an efficient interconnection system, compromises must be made on materials and packing density within acceptable limits, and designers must understand electrical characteristics and the functioning of signal generating devices. High speed digital logic devices are analysed with special attention given to signal swings. Solutions to the problem of line reflection currents are suggested, and the decoupling process is explained. Board design is vitally important and the power and earth distribution contribute strongly towards its success or failure. Power distribution on double‐sided boards is examined, with a consideration of various arrangements of capacitors used for decoupling. After discussion of the effects of other tracks, it is evident that signal tracking lengths should be kept to a minimum, while line impedances are maximised. Guidelines for efficient tracking are provided and an explanation of the trackability factor of a PCB reveals power distribution past the ends of packages to be the most effective arrangement for achieving high packing densities. Double‐sided boards should be used where possible in preference to multilayers.

This paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V.

The analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE.

This paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device.

The proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

The paper presents an efficient methodology that was developed for the reliability prediction and the failure mode effects and criticality analysis (FMECA) of electronic devices using fuzzy logic.

The reliability prediction is based on the general features and characteristics of the MIL‐HDBK‐217FN2 technical document and a derating plan for the system design is developed in order to maintain low components’ failure rates. These failure rates are used in the FMECA, which uses fuzzy sets to represent the respective parameters. A fuzzy failure mode risk index is introduced that gives priority to the criticality of the components for the system operation, while a knowledge base is developed to identify the rules governing the fuzzy inputs and output. The fuzzy inference module is Mamdani type and uses the min‐max implication‐aggregation.

A typical power electronic device such as a switched mode power supply was analyzed and the appropriate reliability indices were estimated using the stress factors of the derating plan. The fuzzy failure mode risk indices were calculated and compared with the respective indices calculated by the conventional FMECA.

Further research efforts are needed for the application of fuzzy modeling techniques in the area of reliability assessment of electronic devices. These research efforts can be concentrated in certain applications that have practical value.

Practical applications can use a fuzzy FMECA modeling instead of the classical FMECA one, in order to obtain a more accurate analysis.

Fuzzy modeling of FMECA is described which can calculate fuzzy failure mode risk indices.