Low power critical voltage transition logic

Abstract

Purpose

To show new design methodology of low power circuit design (Low Power Critical Voltage Transition Logic – LPCVTL) over the conventional CVTL methodology. The comparison is in terms of speed, area and power consumption.

Design/methodology/approach

The new design employs feedback mechanism with a different clocking methodology to overcome high static power dissipation of conventional CVTL design.

Findings

LPCVTL has lower power dissipation property as compared to the conventional CVTL design through the observation of the simulated results of an inverter chain and half adder designs. LPCVTL power dissipation is about eight times smaller than the conventional CVTL.

Research limitation/implications

The desired clock frequency is limited by the output signal response.

Originality/value

LPCVTL is an alternative to dynamic digital IC design methodology which has high speed advantage while maintaining low power consumption.

Citation

Chan, Y.H., Lim, C.C., Lau, K.T. and Foo, S.H. (2006), "Low power critical voltage transition logic", Microelectronics International, Vol. 23 No. 3, pp. 3-8. https://doi.org/10.1108/13565360610680695