A new dual‐rail adiabatic logic family is proposed in this paper. Modified dual‐rail improved adiabatic pseudo domino logic with high throughput (MDIAPDL‐HT) is an improved adiabatic logic design aimed at low power and high throughput performance. The basic structure is the same as the MDIAPDL, but with a different clocking system. This results in power savings up to 95 percent compared to the static CMOS. It has higher throughput with a factor of about four compared to MDIAPDL and a factor of two compared to 4ϕ‐IAPDL.
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