Energy‐recovery low power C‐PAL flip‐flop design

Abstract

Besides combinational circuits, sequential circuits, for instance, flip‐flops, also play an important role in the design of digital systems. In this article, energy‐recovery/adiabatic flip‐flops based on improved PAL‐2N logic with complementary pass transistor logic (CPL) evaluation tree (C‐PAL) family will be described. HSPICE simulation results show that the proposed SR and JK flip‐flops are able to achieve significant power savings compared to the conventional CMOS flip‐flops, with operating frequencies from 50MHz to 250MHz. The supply voltages are scaled down from 5V to 2.5V in order to compare the power consumption with CMOS counterpart. In addition, a 4‐bit binary counter is designed to verify the functionality of the proposed flip‐flops.

Citation

Wong, H.H. and Lau, K.T. (2001), "Energy‐recovery low power C‐PAL flip‐flop design", Microelectronics International, Vol. 18 No. 2, pp. 6-11. https://doi.org/10.1108/13565360110391547