Dual‐rail improved adiabatic pseudo‐domino logic with auxiliary clock: a low‐power partially‐adiabatic CMOS logic family
W.M. Tan
(School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore)
K.T. Lau
(School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore)
290
Abstract
An improved structure for adiabatic pseudo‐domino logic (APDL) family is presented in this paper. The modified dual‐rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.
Keywords
Citation
Tan, W.M. and Lau, K.T. (2003), "Dual‐rail improved adiabatic pseudo‐domino logic with auxiliary clock: a low‐power partially‐adiabatic CMOS logic family", Microelectronics International, Vol. 20 No. 2, pp. 16-18. https://doi.org/10.1108/13565360310472158
Publisher
:MCB UP Ltd
Copyright © 2003, MCB UP Limited