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Analysis and design of lector-based dual-Vt domino logic with reduced leakage current

T.K. Gupta (Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India)
A.K. Pandey (Department of Electronics and Communication, R.K.G.I.T., Ghaziabad, India)
O.P. Meena (Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India)

Circuit World

ISSN: 0305-6120

Article publication date: 7 August 2017

Abstract

Purpose

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.

Design/methodology/approach

In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.

Findings

The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.

Originality/value

The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

Keywords

Citation

Gupta, T.K., Pandey, A.K. and Meena, O.P. (2017), "Analysis and design of lector-based dual-Vt domino logic with reduced leakage current", Circuit World, Vol. 43 No. 3, pp. 97-104. https://doi.org/10.1108/CW-03-2017-0013

Publisher

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Emerald Publishing Limited

Copyright © 2017, Emerald Publishing Limited