The objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraints.
The work has been carried out in two parts. In the first part, simulation results were generated using five different architectures; each designed using four logic design styles for three different transistor sizes. The designs were simulated to generate the values of worst‐case propagation delay and energy consumption per addition. This information is used for validating the delay and energy consumption per addition in the second part.
Optimum adder design under varying condition can be found out using this work.
The predictive model does not consider the variation in load capacitance of each cell.
At present, a prime requirement in application specific integrated circuit design is reduction in design cycle time. As a result, there is minimum scope for exploration of arithmetic units in order to choose the best‐suited design. This work will help the designers to choose an optimum adder design for a given set of requirements.
In this work, four degrees of freedom are taken in adder design space, which are not taken before. Here, the adder design space has been explored, studied, and analyzed in this study under so many varying conditions.
Gupta, A. and Shekhar, C. (2005), "Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders", Microelectronics International, Vol. 22 No. 3, pp. 20-27. https://doi.org/10.1108/13565360510610503Download as .RIS
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