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The set of fuzzy threshold functions is defined to be a fuzzy set over the set of functions. All threshold functions have full memberships in this fuzzy set. Defines and investigates a distance measure between a non‐linearly separable function and the set of all threshold functions. Defines an explicit expression for the membership function of a fuzzy threshold function through the use of this distance measure and finds three upper bounds for this measure. Presents a general method to compute the distance, an algorithm to generate the representation automatically, and a procedure to determine the proper weights and thresholds automatically. Presents the relationships among threshold gate networks, artificial neural networks and fuzzy neural networks. The results may have useful applications in logic design, pattern recognition, fuzzy logic, multi‐objective fuzzy optimization and related areas.

Stochastic computing which is an alternative method of the binary calculation has key merits such as fault-tolerant capability and low hardware cost. However, the hardware response time of it is required to be very fast due to its bit-wise calculation mode. While the complementary metal oxide semiconductor (CMOS) components are difficult to meet the requirements aforementioned. For this, the stochastic computing implementation scheme based on the memristive system is proposed to reduce the response time. The purpose of this paper is to provide the implementation scheme based memristive system for the stochastic computing.

The hardware structure of material logic based on the memristive system is realized according to the advantages of the memristor. After that, the scheme of NOT logic, AND logic and multiplexer are designed, which are the basic units of stochastic computing. Furthermore, a stochastic computing system based on memristive combinational logic is structured and its validity is verified successfully by operating a case.

The numbers of the elements of the proposed stochastic computing system are less than the conventional stochastic computing based on CMOS circuits.

The paper proposed a novel implementation scheme for stochastic computing based on the memristive systems, which are different from the conventional stochastic computing based on CMOS circuits.

The purpose of this paper is to present a single-precision floating-point multiplier where a low-power operation is attained through the reduction of switching activity. A floating-point multiplier is the basic building block for many applications such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range.

A floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail delay insensitive logic (MTD³L). The proposed logic deals with high performance and energy efficiency.

The Institute of Electrical and Electronics Engineering (IEEE) has provided a standard to define the floating-point representation, which is known as the IEEE 754 standard. Rounding has not been implemented because it is not suitable for high-precision applications.

The performance aspects of the proposed asynchronous MTD³L floating-point multiplier are obtained using a Mentor Graphics tool and are compared with those of the existing asynchronous logic.

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.

In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.

The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.

The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

This paper is an attempt to bridge the gap between, on the one hand, the mobility behaviour of households and their perception of accessibility to urban amenities and, on the other hand, house price dynamics as captured through hedonic modelling.

In order to analyse the mobility behaviour of individuals and households, their sensitivity to travel time from home to service places is estimated so as to assess their perceived accessibility, using “subjective” indices based on actual trips, as reported in the 2001 origin‐destination survey designed for Quebec City. For comparative purposes, both objective and subjective accessibility indices based, in the former case on observed travel times and, in the latter case on fuzzy logic criteria, are computed and used as a complement to a centrality index in a hedonic model of house prices.

Findings indicate that there are statistically significant differences in the way accessibility is structured depending on trip purposes and household profiles. They also suggest that, while an objective measure of accessibility yields good results, resorting to subjective, and more comprehensive, accessibility indices derived from fuzzy logic provides greater insight into the understanding of commuting patterns and travel behaviour of people.

Better understanding the complexity of individuals’ and households’ mobility behaviour should result in more adequate initiatives and decisions being taken by transportation and city planning authorities.

Accessibility to jobs and services has long been known as a major determinant of urban, residential and non residential, rents. Yet, it is more often than not assumed to derive from a rather straightforward process, which this paper shows is not the case.

The general problem to be considered in this paper is as follows: Given a general system defined by m attributes, find a meaningful partition of systems’ behaviors. Using an order preserving mapping from a space of m attributes into an m‐dimensional Euclidean space, a partitioning criterion of systems' behaviors is defined. Then, its mathematical properties are studied, on the basis of the usual hyperplane separation theorem and of the existence theorem of ton Neumann and Morgenstern's utility function.

The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture.

A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system.

The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images.

This research brings about a new direction in the development of edge detection, in terms of developing high-speed parallel processing edge detection and imaging circuits.

The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering.

This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.

A fuzzy symmetric threshold (ST) function is defined to be a fuzzy set over the set of functions. All ST functions have full memberships in this fuzzy set. For n variables, there are (2n+2) ST functions. A distance measure between a nonsymmetric threshold function and the set of all ST functions is defined and investigated. An explicit expression for the membership function of a fuzzy ST function is defined through the use of this distance measure. An algorithm for obtaining this distance measure is presented with illustrative examples. It is also shown that any function and its complement always have the same grade of membership in the class of fuzzy ST functions. Applications to concise function representation and simple function implementation are also presented with examples. In addition, most inseparable unsymmetric functions are defined and investigated. Fuzzy ST functions are relevant to the development of practical applications of fuzzy methods and might contribute to the state of the art in the implementations of fuzzy methods in the areas requiring utilization of ST functions.

Focuses on integrating the theory and practice of organizational transformation through the metaphors of chaos theory and self‐organization. Case study data were collected through in‐depth interviews of three practitioner/theorists ‐ Peter Senge, William Torbert and Ellen Wingard ‐ all of whom have formulated theories of organizational change which they use as practitioners for generating transformations in organizations. The interviews suggest that all three of them utilize the logic of their (very different) theories to rationally set up the conditions for organizational change, but that the transformations they describe were sparked not through rational efforts but, in their words, through “grace”, “magic”, and “a miracle”. The new sciences of chaos and self‐organization provide a number of useful metaphors that can help us understand these non‐linear events. Describes the case studies in some depth and then identifies commonalities across the interventions in terms of a three‐phase model of dynamic order, thresholds at the edge of logic, and the self‐organized emergence of new order. Uses metaphors from new science to explain this process, aiming to identify a “chaotic logic” that links rational theory and intuitive practice in transformations of groups and organizations.

The real-time generation of feature descriptors for object recognition is a challenging problem. In this research, the purpose of this paper is to provide a hardware friendly framework to generate sparse features that can be useful for key feature point selection, feature extraction, and descriptor construction. The inspiration is drawn from feature formation processes of the human brain, taking into account the sparse, modular, and hierarchical processing of visual information.

A sparse set of neurons referred as active neurons determines the feature points necessary for high-level vision applications such as object recognition. A psycho-physical mechanism of human low-level vision relates edge detection to noticeable local spatial stimuli, representing this set of active neurons. A cognitive memory cell array-based implementation of low-level vision is proposed. Applications of memory cell in edge detection are used for realizing human vision inspired feature selection and leading to feature vector construction for high-level vision applications.

True parallel architecture and faster response of cognitive circuits avoid time costly and redundant feature extraction steps. Validation of proposed feature vector toward high-level computer vision applications is demonstrated using standard object recognition databases. The comparison against existing state-of-the-art object recognition features and methods shows an accuracy of 97, 95, 69 percent for Columbia Object Image Library-100, ALOI, and PASCAL VOC 2007 databases indicating an increase from benchmark methods by 5, 3 and 10 percent, respectively.

A hardware friendly low-level sparse edge feature processing system is proposed for recognizing objects. The edge features are developed based on threshold logic of neurons, and the sparse selection of the features applies a modular and hierarchical processing inspired from the human neural system.