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This study aims to improve the complexity of chaotic systems and the security accuracy of information encrypted transmission. Applying five-dimensional memristive Hopfield neural network (5D-HNN) to secure communication will greatly improve the confidentiality of signal transmission and greatly enhance the anticracking ability of the system.

Chaos masking: Chaos masking is the process of superimposing a message signal directly into a chaotic signal and masking the signal using the randomness of the chaotic output. Synchronous coupling: The coupled synchronization method first replicates the drive system to get the response system, and then adds the appropriate coupling term between the drive The synchronization error and the coupling term of the system will eventually converge to zero with time. The synchronization error and coupling term of the system will eventually converge to zero over time.

A 5D memristive neural network is obtained based on the original four-dimensional memristive neural network through the feedback control method. The system has five equations and contains infinite balance points. Compared with other systems, the 5D-HNN has rich dynamic behaviors, and the most unique feature is that it has multistable characteristics. First, its dissipation property, equilibrium point stability, bifurcation graph and Lyapunov exponent spectrum are analyzed to verify its chaotic state, and the system characteristics are more complex. Different dynamic characteristics can be obtained by adjusting the parameter k.

A new 5D memristive HNN is proposed and used in the secure communication

Stochastic computing which is an alternative method of the binary calculation has key merits such as fault-tolerant capability and low hardware cost. However, the hardware response time of it is required to be very fast due to its bit-wise calculation mode. While the complementary metal oxide semiconductor (CMOS) components are difficult to meet the requirements aforementioned. For this, the stochastic computing implementation scheme based on the memristive system is proposed to reduce the response time. The purpose of this paper is to provide the implementation scheme based memristive system for the stochastic computing.

The hardware structure of material logic based on the memristive system is realized according to the advantages of the memristor. After that, the scheme of NOT logic, AND logic and multiplexer are designed, which are the basic units of stochastic computing. Furthermore, a stochastic computing system based on memristive combinational logic is structured and its validity is verified successfully by operating a case.

The numbers of the elements of the proposed stochastic computing system are less than the conventional stochastic computing based on CMOS circuits.

The paper proposed a novel implementation scheme for stochastic computing based on the memristive systems, which are different from the conventional stochastic computing based on CMOS circuits.

The purpose of this paper is to construct a proportion-integral-type (PI-type) memristor, which is different from that of the previous memristor emulator, but the constructing memristive chaotic circuit possesses line equilibrium, leading to the emergence of the initial conditions-related dynamical behaviors.

This paper presents a PI-type memristor emulator-based canonical Chua’s chaotic circuit. With the established mathematical model, the stability region for the line equilibrium is derived, which mainly consists of stable and unstable regions, leading to the emergence of bi-stability because of the appearance of a memristor. Initial conditions-related dynamical behaviors are investigated by some numerically simulated methods, such as phase plane orbit, bifurcation diagram, Lyapunov exponent spectrum, basin of the attraction and 0-1 test. Additionally, PSIM circuit simulations are executed and the seized results validate complex dynamical behaviors in the proposed memristive circuit.

The system exhibits the bi-stability phenomenon and demonstrates complex initial conditions-related bifurcation behaviors with the variation of system parameters, which leads to the occurrence of the hyperchaos, chaos, quasi-periodic and period behaviors in the proposed circuit.

These memristor emulators are simple and easy to physically fabricate, which have been increasingly used for experimentally demonstrating some interesting and striking dynamical behaviors in the memristor-based circuits and systems.

An annual substation equipment failure report says 3/7 capacitive voltage transformer (CVT) got damaged because of ferroresonance overvoltage. The conventional mitigation circuit fails to protect the transformer as the overvoltage may fall in the range between 2 and 4 per unit. It is necessary to develop a device to suppress the overvoltage as well as overcurrent of the CVT. This study aims to propose the suitability of memristor emulator as a mitigation circuit for ferroresonance.

The literature implies that a nonlinear circuit can protect the transformer against ferroresonance. An attempt is made with a memristor emulator using Operational Amplifier (OPAMP) for the mitigation of ferroresonance in a prototype transformer. The circuit is simulated using PSpice and validated for its ideal characteristics using hardware implementation. The nonlinear memductance is designed which is required to mitigate the ferroresonance. The mitigation performance has been compared with conventional method along with fast Fourier transform (FFT) analysis.

While the linear resistor recovers the secondary voltage by 74.1%, the memristor emulator does it by 82.05% during ferroresonance. Also, the total harmonic distortion (THD) of ferroresonance signal found to be 22.06% got improved as 2.56% using memristor emulator.

The suitability of memristor emulator as a mitigation circuit for ferroresonance is proposed in this paper. As ferroresonance occurs in instrument transformers which have extra high voltage (EHV) rated primary windings and (110 V/[110 V/1.732]) rated secondary windings, the mitigation device is proposed to be connected as a nonlinear load across the secondary windings of the transformer. This paper discusses the preliminary work of ferroresonance mitigation in a prototype transformer. The mitigation circuit may have memristor or meminductor for ferroresonance mitigation when they are commercially available in future.

The electronic component-based memristor emulator may not work at 110 V practically as they may be rated at low power. Hence, chemical component-based memristor emulator was developed to do the same. The authors like to clarify that the memristor will be a solution for ferroresonance in future not the memristor emulator circuit.

With the real form of memristor, the transistor world will be replaced by it and may have a revolution in the field of electronics, VLSI, etc. This contribution attempts to project the use of memristor in a smaller scale in high-voltage engineering.

The electronic component-based memristor emulator is proposed as a mitigation circuit for ferroresonance. The hypothesis has been verified successfully in a prototype transformer. Testing circuit of memristor emulator involves transformer, practically. The mitigation performance has been compared with conventional method technically and justified with FFT analysis.

The ammeter can measure the direct current and low-frequency alternating current through the wires, but it is difficult to measure complex waveforms. The oscilloscope can measure complex waveforms, but it is easy to measure the voltage waveform and difficult to measure the current waveform. Thus, how to measure complex current waveforms with oscilloscope is an important and crucial issue that needs to be solved in practical engineering applications. To solve the above problems, an active short circuit line method is proposed to measure the volt-ampere characteristic curve of chaotic circuits.

In this paper, an active short circuit line method is proposed to measure the volt-ampere characteristic curve of various chaotic circuits especially for memristive systems. A memristor-based chaotic system is introduced, and the corresponding memristor-based circuit is constructed and implemented by using electronic components.

The chaotic attractors and volt-ampere characteristic curve of the memristor-based chaotic circuit are successfully analyzed and verified by oscilloscope measurement with the proposed active short circuit line method. Accordingly, the hardware circuit experiments are carried out to validate the effectiveness and feasibility of the active short circuit line method for these chaotic circuits. A good agreement is shown between the numerical simulations and the experimental results.

The primary contributions of this paper are as follows: an active short circuit line method for measuring the volt-ampere characteristic curve of chaotic circuits is proposed for the first time. A memristor-based chaotic system is also constructed by using memristor as nonlinear term. Then, the active short circuit line method is applied to measure the volt-ampere characteristic curve of the corresponding memristor-based chaotic circuit.

The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.

The real-time generation of feature descriptors for object recognition is a challenging problem. In this research, the purpose of this paper is to provide a hardware friendly framework to generate sparse features that can be useful for key feature point selection, feature extraction, and descriptor construction. The inspiration is drawn from feature formation processes of the human brain, taking into account the sparse, modular, and hierarchical processing of visual information.

A sparse set of neurons referred as active neurons determines the feature points necessary for high-level vision applications such as object recognition. A psycho-physical mechanism of human low-level vision relates edge detection to noticeable local spatial stimuli, representing this set of active neurons. A cognitive memory cell array-based implementation of low-level vision is proposed. Applications of memory cell in edge detection are used for realizing human vision inspired feature selection and leading to feature vector construction for high-level vision applications.

True parallel architecture and faster response of cognitive circuits avoid time costly and redundant feature extraction steps. Validation of proposed feature vector toward high-level computer vision applications is demonstrated using standard object recognition databases. The comparison against existing state-of-the-art object recognition features and methods shows an accuracy of 97, 95, 69 percent for Columbia Object Image Library-100, ALOI, and PASCAL VOC 2007 databases indicating an increase from benchmark methods by 5, 3 and 10 percent, respectively.

A hardware friendly low-level sparse edge feature processing system is proposed for recognizing objects. The edge features are developed based on threshold logic of neurons, and the sparse selection of the features applies a modular and hierarchical processing inspired from the human neural system.

This paper aims to propose the modeling of nanostructured memristor, and the circuit of amplitude modulator was designed and analyzed with memristor. The simulation results show that the nanostructured memristor can be utilized to implement the desired amplitude modulated signal.

The modeling of nanostructured memristor is proposed in this paper, and the circuit of amplitude modulator was designed and analyzed with memristor, amplifiers and BPF device. For measuring the modulated signal, the emulator circuit of memristor is designed. The simulation results show that the nanostructured memristor can be utilized to implement the desired amplitude modulated signal.

The innovations of this work are as follows: the AM modulator circuit using memristor has been proposed, analyzed and simulated. The emulator of memristor is given.

The innovations of this work are as follows: the AM modulator circuit using memristor has been proposed, analyzed and simulated. The emulator of memristor is given, and the results of this work demonstrate that the nonlinearity of the memristor can be used to generate the desired amplitude modulation free of harmonic sidebands, because of distortion of the modulating signal.

The purpose of this paper is to construct a multiwing chaotic system that has hidden attractors with multiple stable equilibrium points. Because the multiwing hidden attractors chaotic systems are safer and have more dynamic behaviors, it is necessary to construct such a system to meet the needs of developing engineering.

By introducing a multilevel pulse function into a three-dimensional chaotic system with two stable node–foci equilibrium points, a hidden multiwing attractor with multiple stable equilibrium points can be generated. The switching behavior of a hidden four-wing attractor is studied by phase portraits and time series. The dynamical properties of the multiwing attractor are analyzed via the Poincaré map, Lyapunov exponent spectrum and bifurcation diagram. Furthermore, the hardware experiment of the proposed four-wing hidden attractors was carried out.

Not only unstable equilibrium points can produce multiwing attractors but stable node–foci equilibrium points can also produce multiwing attractors. And this system can obtain 2N + 2-wing attractors as the stage pulse of the multilevel pulse function is N. Moreover, the hardware experiment matches the simulation results well.

This paper constructs a new multiwing chaotic system by enlarging the number of stable node–foci equilibrium points. In addition, it is a nonautonomous system that is more suitable for practical projects. And the hardware experiment is also given in this article which has not been seen before. So, this paper promotes the development of hidden multiwing chaotic attractors in nonautonomous systems and makes sense for applications.

With the development of integrated circuit and communication technology, digital secure communication has become a research hotspot. This paper aims to design a five-dimensional fractional-order chaotic secure communication circuit with sliding mode synchronous based on microcontroller (MCU).

First, a five-dimensional fractional-order chaotic system for encryption is constructed. The approximate numerical solution of fractional-order chaotic system is calculated by Adomian decomposition method, and the phase diagram is obtained. Then, combined with the complexity and 0–1 test algorithm, the parameters of fractional-order chaotic system for encryption are selected. In addition, a sliding mode controller based on the new reaching law is constructed, and its stability is proved. The chaotic system can be synchronized in a short time by using sliding mode control synchronization.

The electronic circuit is implemented to verify the feasibility and effectiveness of the designed scheme.

It is feasible to realize fractional-order chaotic secure communication using MCU, and further reducing the synchronization error is the focus of future work.